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MC74HC240AFL1-MC74HC240AFR1
Octal With 3-State Outputs Inverting Buffer/Line Driver/Line Receiver
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High–Performance Silicon–Gate CMOSThe MC74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3–state memory address drivers, clock drivers, and
other sub–oriented systems. The device has inverting outputs and two
active–low output enables.
The HC240A is similar in function to the HC244A. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 120 FETs or 30 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTS YB4
YB3
YB2
YB1
YA4
YA3
YA2
YA1
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GNDOUTPUT
ENABLES
ENABLE A
ENABLE B
FUNCTION TABLE
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
TSSOP–20
DT SUFFIX
CASE 948E
ORDERING INFORMATION
PIN ASSIGNMENTYB4
ENABLE A
GND
YB1
YB2
YB3
YA2
YA1
ENABLE B
VCC
YA4
YA3
