MC74AC273D ,Octal D Flip-Flopsetup time before the LOW–to–HIGH clock transition, is transferredto the corresponding flip–flop’s ..
MC74AC273DTR2 ,Octal D-Type Flip-Flop compatible InputsMC74AC273, MC74ACT273Octal D Flip-FlopThe MC74AC273/74ACT273 has eight edge-triggered D–typeflip–fl ..
MC74AC273DTR2G , Octal D Flip−Flop
MC74AC273DWR2 ,Octal D-Type Flip-Flop compatible InputsMaximum Ratings are those values beyond which damage to the device may occur. Functional operation ..
MC74AC273N ,OCTAL D FLIP-FLOP* ** * OCTAL D FLIP-FLOPThe MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with indi ..
MC74AC299DWR2 ,8-Input Universal Shift/Storage Register with Common Parallel I/O Pins3MC74AC299, MC74ACT299DC CHARACTERISTICS 74AC 74ACT =AVCCSymbol Parameter T = +25°C −40°C to Unit ..
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MCP1541 , 2.5V AND 4.096V VOLTAGE REFERENCES
MCP2140 , Infrared Encoder/Decoder
MCP2551 , High-Speed CAN Transceiver
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MC74AC273D
Octal D Flip-Flop
MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D–type
flip–flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip–flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW–to–HIGH clock transition, is transferred
to the corresponding flip–flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements. Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip–Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version Outputs Source/Sink 24 mA ′ACT273 Has TTL Compatible Inputs
Figure 1. Pinout: 20–Lead Packages Conductors(Top View)
VCC D7 D6 Q6 Q5 D5 D4 Q4 CP Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN ASSIGNMENT
