MC14LC5472FU ,U-interface transceiverLOGIC DIAGRAM1 24OE1 OE2OE1 1 48 LE148 25O0 2 47 D0LE1 LE2O1 3 46 D1 2 13nLE nLEO0 O847 Q 36 QGND 4 ..
MC14LC5472FU ,U-interface transceiver**SEMICONDUCTOR TECHNICAL DATA*##!’ * * ’%*"&$*% * *"’ **’ ’* #!*%*"’ * *"$(’& *"* *(’$(’&*’*’** *# ..
MC14LC5480DW ,5 V PCM Codec-FilterBlock DiagramDEVICE DESCRIPTION which increment. When the chord bits increment, the stepbits double ..
MC14LC5480P ,5 V PCM Codec-FilterBlock DiagramDEVICE DESCRIPTION which increment. When the chord bits increment, the stepbits double ..
MC14LC5480SD ,5 V PCM Codec-FilterBlock DiagramDEVICE DESCRIPTION which increment. When the chord bits increment, the stepbits double ..
MC14LC5540DW ,ADPCM Codecfeatures.321The ADPCM Codec is designed to meet the 32 kbps ADPCM conformancerequirements of CCITT ..
MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F11D ,TRIPLE 3-INPUT AND GATE FAST SCHOTTKY TTL
MC74F1245N ,OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS
MC74F1245N ,OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS
MC74F125 ,3-STATE QUAD BUFFERSMC54/74F125MC54/74F1263-STATE QUAD BUFFERS• High Impedance NPN Base Inputs for Reduced LoadingQUAD ..
MC14LC5472FE-MC14LC5472FU
U-interface transceiver
SEMICONDUCTOR TECHNICAL DATA#*#!’ ’%"&$%"’ ’
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The MC74LCX16373 is a high performance, non–inverting 16–bit
transparent latch operating from a 2.7 to 3.6V supply. The device is byte
controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16–bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX16373 inputs to be safely driven from 5V devices.
The MC74LCX16373 contains 16 D–type latches with 3–state
5V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data
on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH–to–LOW
transition of LE. The 3–state outputs are controlled by the Output Enable
(OEn) inputs. When OE is LOW, the outputs are enabled. When OE is
HIGH, the standard outputs are in the high impedance state, but this does
not interfere with new data entering into the latches. Designed for 2.7 to 3.6V VCC Operation 5.4ns Maximum tpd 5V T olerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20μA)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500mA ESD Performance: Human Body Model >2000V; Machine Model >200V
PIN NAMES
