MC14526BCL ,Presettable 4-bit down counterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14526BCL ,Presettable 4-bit down counter**SEMICONDUCTOR TECHNICAL DATA** * * * * **The MC14522B BCD counter and the MC14526B binary counte ..
MC14526BCP ,Presettable 4-bit down counterMAXIMUM RATINGS* (Voltages Referenced to V )SSMC14XXXBDW SOICSymbol Parameter Value UnitT = – 55° t ..
MC14527BCL ,BCD Rate MultiplierMaximum Ratings are those values beyond which damage to the device may occur. SÎÎÎ12 7CASC Eout†Tem ..
MC14527BCL ,BCD Rate Multiplier**SEMICONDUCTOR TECHNICAL DATA ** * *The MC14527B BCD rate multiplier (DRM) provides an output pul ..
MC14527BCL ,BCD Rate MultiplierBLOCK DIAGRAMT Storage Temperature – 65 to + 150 * CÎÎstg4T Lead Temperature (8–Second Soldering) 2 ..
MC68HC908QT1CP ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 1536 bytes
MC68HC908QT4CDW ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 4096 bytes, ADC
MC68HC908QT4CDW ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 4096 bytes, ADC
MC68HC908QT4CP ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 4096 bytes, ADC
MC68HC908QT4CP ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 4096 bytes, ADC
MC68HC908QT4CP ,High-performance M68HC08 family of 8-bit microcontroller units (MCUs), (CISC) with a von neumann architecture, FLASH memory 4096 bytes, ADC
MC14526BCL-MC14526BCP
Presettable 4-bit down counter
-The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters
with a decoded “0” state output for divide–by–N applications. In single stage
applications the “0” output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
These complementary MOS counters can be used in frequency synthesiz-
ers, phase–locked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity. Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition of Inhibit Asynchronous Preset Enable Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
FUNCTION TABLEX = Don’t Care
NOTES:
*Output “0” is low when reset goes high only it PE and CF are low.
**Output “0” is high when reset is low, only if CF is high and count is 0000.
SEMICONDUCTOR TECHNICAL DATA
