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MC14042BCL-MC14042BCP Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
MC14042BCLMOT?N/a230avaiQuad transparent latch
MC14042BCLMOTOROLAN/a16avaiQuad transparent latch
MC14042BCLMOTN/a300avaiQuad transparent latch
MC14042BCPMOTN/a1048avaiQuad Latch


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MC14042BCL-MC14042BCP
Quad transparent latch
-The MC14042B Quad Transparent Latch is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity input.
Information present at the data input is transferred to outputs Q and Q during
the clock level which is determined by the polarity input. When the polarity
input is in the logic “0” state, data is transferred during the low clock level,
and when the polarity input is in the logic “1” state the transfer occurs during
the high clock level. Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
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ÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
LOGIC DIAGRAM

CLOCK
POLARITY
VDD = PIN 16
VSS = PIN 8
SEMICONDUCTOR TECHNICAL DATA
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