MC14027BFL1 ,Dual J-K Flip-FlopELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14028BCL ,Binary-to-octal decoderMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14028BCP ,BCD-to-Decimal DecoderMAXIMUM RATINGS* (Voltages Referenced to V )SS T = – 55° to 125°C for all packages.AÎÎSymbol Parame ..
MC14028BCPG , BCD−To−Decimal Decoder Binary−To−Octal Decoder
MC14028BDR2 ,BCD-to-Decimal DecoderMaximum Ratings are those values beyond which damage to the deviceMC14028BCP PDIP–16 2000/Boxmay oc ..
MC14028BDR2G , BCD−To−Decimal Decoder Binary−To−Octal Decoder
MC68332AVFC16 ,32-Bit Modular MicrocontrollerFeatures ........51.2
MC68332AVFC16 ,32-Bit Modular Microcontroller Order this documentMOTOROLAby MC68332TS/D Rev. 2SEMICONDUCTORTECHNICAL DATAMC68332Techni ..
MC68332CFC16 ,32-Bit Modular MicrocontrollerFeatures ........51.2
MC68332GCEH20 , 32-Bit Modular Microcontroller
MC68332GCEH-20 , 32-Bit Modular Microcontroller
MC68332GCEH25 , 32-Bit Modular Microcontroller
MC14027BFL1
Dual J-K Flip-Flop
--The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Swing Independent of Fanout Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range Pin–for–Pin Replacement for CD4027B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
