MC14018BCP ,Presettable divide-by-N counterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ − 55CÎÎ 25CÎÎÎÎÎ 125CÎÎÎV VDDChar ..
MC14018BF ,Presettable Divdie-By-N CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14018BFEL ,Presettable Divdie-By-N Counter3MC14018B(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25* C)L AÎÎÎÎ All TypesÎÎÎV VDD DD(8. ..
MC14018BFR1 ,Presettable Divide-By-N CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14020B ,14-Bit Binary CounterMAXIMUM RATINGS (Voltages Referenced to V )SS14TSSOP−16Symbol Parameter Value UnitDT SUFFIX 020BCAS ..
MC14020BCL ,14-bit binary counterMAXIMUM RATINGS* (Voltages Referenced to V )SSMC14XXXBD SOICÎÎSymbol Parameter Value UnitT = – 55° ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerMAXIMUM RATINGSI Rating Symbol Value oi,"F (hoc?" Veltige " - - VCC - - l) 5107* 7 CL. - Vdci_ inpm ..
MC6828P ,V(cc): -0.5 to +7.0V; priority interrupt controllerBLOCK DIAGRAMLatched InputsW 11 o- 1-of-8[NS IO o--- Priority VectorDi? 9 th---- B-Bit Encoder Look ..
MC68302CFC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FC16 ,Integrated Multiprotocol Processor User痵 ManualGeneral DescriptionSection 2 MC68000/MC68008 CoreSection 3 System Integration Block (SIB)Section 4 ..
MC68302FE16 ,Integrated multiprotocol processor (IMP). Frequency 16.67 MHz.Order this documentDEC 1 2 1990 by MC68302/DMOTOROLA_ TECHNICAL DATAF MC68302Integrated Multiprotoc ..
MC68302RC ,Integrated multiprotocol processor (IPM).MOTOROLA- SEMICONDUCTOR -l-lll-il-ig-IigtTECHNICAL DATAMC68302Technical c, ImmaruIntegrateThe IMP i ..
MC14018BCP
Preset Divide By N Counter
MC14018B
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are
synchronous, and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input.
Data on the Jam inputs will then be transferred to their respective Q
outputs (inverted). A logic 1 on the reset input will cause all Q outputs
to go to a logic 1 state.
Division by any number from 2 to 10 can be accomplished by
connecting appropriate Q outputs to the data input, as shown in the
Function Selection table. Anti−lock gating is included in the
MC14018B to assure proper counting sequence.
Features Fully Static Operation Schmitt Trigger on Clock Input Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range Pin−for−Pin Replacement for CD4018B Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
