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MC14015BCLMOTOROLAN/a40avaiDual 4-bit static shift register
MC14015BCLMOTN/a450avaiDual 4-bit static shift register
MC14015BCLMOT?N/a120avaiDual 4-bit static shift register
MC14015BCPMOTOROLAN/a753avaiDual 4-bit static shift register


MC14015BCP ,Dual 4-bit static shift registerMaximum Ratings are those values beyond which damage to the device may occur. 15 DQ1 12†Temperature ..
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MC14015BF ,Dual 4-Bit Static Shift RegisterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
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MC14015BFR1 ,Dual 4-Bit Static Shift RegisterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
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MC14015BCL-MC14015BCP
Dual 4-bit static shift register
-The MC14015B dual 4–bit static shift register is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. It consists of two identical, independent 4–state
serial–input/parallel–output registers. Each register has independent Clock
and Reset inputs with a single serial Data input. The register states are type
D master–slave flip–flops. Data is shifted from one stage to the next during
the positive–going clock transition. Each register can be cleared when a high
level is applied on the Reset line. These complementary MOS shift registers
find primary use in buffer storage and serial–to–parallel conversion where
low power dissipation and/or noise immunity is desired. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going edge
of the clock pulse. Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
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ÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
TRUTH TABLE

X = Don’t Care
Qn = Q0, Q1, Q2, or Q3, as applicable.
Qn–1 = Output of prior stage.
SEMICONDUCTOR TECHNICAL DATA
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