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MC100H601ONN/a36avai9-Bit ECL-TTL Translator
MC10H601MOTN/a27avai9-Bit ECL-TTL Translator
MC10H601FNR2MOTN/a290avai9-Bit ECL-TTL Translator


MC10H601FNR2 ,9-Bit ECL-TTL Translator3MC10H601, MC100H601AC CHARACTERISTICS: V = 5.0 V ± 10%; V = −5.2 V ± 5% (10H version); V = −4.2 V ..
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MC44460B ,PICTURE-IN-PICTURE (PIP) CONTROLLERBlock DiagramDecoder Clamp CapsSync Out Filter PLL ADC Mid–Ref28 33 40 41 42 5129FilterSync InLow P ..
MC44460B ,PICTURE-IN-PICTURE (PIP) CONTROLLERELECTRICAL CHARACTERISTICS (V = V = 5.0 V, T = 25°C, unless otherwise noted.)CC DD AÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ..
MC44461B ,PICTURE-IN-PICTURE (PIP) CONTROLLERELECTRICAL CHARACTERISTICS (continued) (V = V = 5.0 V, T = 25°C, unless otherwise noted.)CC DD ACha ..
MC44462B ,Y-C PICTURE-IN-PICTURE (PIP) CONTROLLERELECTRICAL CHARACTERISTICS (continued) (V = V = 5.0 V, T = 25°C, unless otherwise noted.)CC DD ACha ..
MC44463B ,REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLERELECTRICAL CHARACTERISTICS (V = V = 5.0 V, T = 25°C, unless otherwise noted.)CC DD ACharacteristic ..
MC44602P2 ,HIGH PERFORMANCE CURRENT MODE CONTROLLERfeatures consist of input and reference undervoltagelockouts each with hysteresis, cycle–by–cycle c ..


MC100H601-MC10H601-MC10H601FNR2
9-Bit ECL-TTL Translator
MC10H601, MC100H601
9-Bit ECL� to �TTL T ranslator
The MC10H/100H601 is a 9−bit, dual supply ECL to TTL
translator. Devices in the Motorola 9−bit translator series utilize the
28−lead PLCC for optimal power pinning, signal flow−through and
electrical performance.
The devices feature a 48 mA TTL output stage, and AC
performance is specified into both a 50 pF and 200 pF load
capacitance. For the 3−state output disable, both ECL and TTL control
inputs are provided, allowing maximum design flexibility.
The 10H version is compatible with MECL 10H ECL logic levels.
The 100H version is compatible with 100K levels. 9−Bit Ideal for Byte−Parity Applications 3−State TTL Outputs Flow−Through Configuration Extra TTL and ECL Power Pins to Minimize Switching Noise ECL and TTL 3−State Control Inputs Dual Supply 4.8 ns Max Delay into 50 pF, 9.6 ns into 200 pF (all Outputs
Switching) PNP TTL Inputs for Low Loading
ORDERING INFORMATION
MARKING
DIAGRAM
= Assembly Location = Wafer Lot = Year = Work Week
PLCC−28
FN SUFFIX
CASE 776

PIN NAMES

VCCT
GND
VCCEGN
VCCTQ6 GNDQ7Q8
OETTL NC OEECLVEED0D1 D2
Pinout: 28−Lead PLCC (Top View)
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