MC10H351MEL ,TTL, NMOS To ECL Translator2MC10H351PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
MC10H351MEL ,TTL, NMOS To ECL TranslatorELECTRICAL CHARACTERISTICS (V = V = V = 5.0 V ± 5.0%)†CC CC1 CC20° 25° 75°Symbol Characteristic Min ..
MC10H351MEL ,TTL, NMOS To ECL Translator
MC10H351MEL ,TTL, NMOS To ECL TranslatorPrepared by: Paul ShockmanON SemiconductorAPPLICATION NOTEObjectiveGeneral BackgroundThis applicati ..
MC10H351ML1 ,Quad TTL/NMOS to PECL* Translator**SEMICONDUCTOR TECHNICAL DATA* ** ** **L SUFFIXCERAMIC PACKAGEThe MC10H351 is a quad translator fo ..
MC10H351P ,Quad TTL/NMOS to PECL TranslatorAPPLICATION NOTEDifferential Characteristics (continued)APPLICATION NOTE USAGEThis application note ..
MC44144 ,SUBCARRIER PHASE-LOCKED LOOPELECTRICAL CHARACTERISTICS (V = 5.0 Vdc, T = 25°C)CC ACharacteristic Pin Min Typ Max UnitOperating ..
MC44144 ,SUBCARRIER PHASE-LOCKED LOOPFunctional Description text.Figure 1. Typical VCXO Gain14.322 17.745KOPALTable 1. Crystal Specifica ..
MC44144 ,SUBCARRIER PHASE-LOCKED LOOPMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V 6.0 VdcCCOperating Ambient Temperature T 0 ..
MC44144D ,SUBCARRIER PHASE-LOCKED LOOPFunctional Description text.Figure 1. Typical VCXO Gain14.322 17.745KOPALTable 1. Crystal Specifica ..
MC44144P ,SUBCARRIER PHASE-LOCKED LOOPOrder this document by MC44144/D** *The MC44144 is a gated phase–locked loop intended for, but not ..
MC44145D ,PIXEL CLOCK GENERATOR/ SYNC SEPARATOROrder this document by MC44145/D ** ** The MC44145, Pixel Clock Generator, is a component of the MC ..
MC10H351MEL
TTL, NMOS To ECL Translator
---The MC10H351 is a quad translator for interfacing data between a
saturated logic section and the PECL section of digital systems when
only a +5.0 Vdc power supply is available. The MC10H351 has
TTL/NMOS compatible inputs and PECL complementary
open–emitter outputs that allow use as an inverting/non–inverting
translator or as a differential line driver. When the common strobe
input is at a low logic level, it forces all true outputs to the PECL low
logic state (≈ +3.2 V) and all inverting outputs to the PECL high logic
state (≈ +4.1 V).
The MC10H351 can also be used with the MC10H350 to transmit
and receive TTL/NMOS information differentially via balanced
twisted pair lines. Single +5.0 Power Supply All VCC Pins Isolated On Chip Differentially Drive Balanced Lines tpd = 1.3 nsec Typical
LOGIC DIAGRAM
DIP PIN ASSIGNMENTB OUT
B OUT
N.C.
A OUT
A OUT
VCC
B IN
A IN
ECL VCC
C OUT
C OUT
D OUT
D OUT
VCC 2
C IN
N.C.
COMMON
STROBE
GND
D IN
TTL VCC 19 16 5
B IN
A IN
COMMON
STROBE
D IN
C IN
B OUT
B OUT
A OUT
A OUT
D OUT
D OUT
C OUT
C OUT
VCC (+5.0 VDC) = PINS 6, 11, 15, 20
GND = PIN 10
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–20
L SUFFIX
CASE 732
PDIP–20
P SUFFIX
CASE 738
PLCC–20
FN SUFFIX
CASE 775
