MC10H334 ,Quad Bus Driver/Receiver Translator3MC10H334PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
MC10H334FN ,Quad Bus Driver/Receiver TranslatorMAXIMUM RATINGSPIN ASSIGNMENTCharacteristic Symbol Rating UnitPower Supply (V = 0) V –8.0 to 0 VdcC ..
MC10H334FN ,Quad Bus Driver/Receiver TranslatorPrepared byCleon PettyAPPLICATION NOTETodd PearsonECL Applications EngineeringThis application note ..
MC10H334FN ,Quad Bus Driver/Receiver TranslatorELECTRICAL CHARACTERISTICS (V = –5.2 V ±5%) (See Note) 6 15EE0° 25° 75°DLE 7 14 RLECharacteristic S ..
MC10H334L ,Quad Bus Driver/Receiver with Transmit and Receiver Latches**SEMICONDUCTOR TECHNICAL DATA* ** * ** The MC10H334 is a Quad Bus Driver/Receiver with transmit ..
MC10H334L ,Quad Bus Driver/Receiver with Transmit and Receiver LatchesELECTRICAL CHARACTERISTICS (V = –5.2 V ±5%) (See Note) 6 15EE0° 25° 75°DLE 7 14 RLECharacteristic S ..
MC4316L ,Programmable modulo-N counter(13) MOTOROLAPROGRAMMABLE MODULO-N COUNTERSThe monolithic devices are programmable, cascadable,modu ..
MC4324L ,DUAL VOLTAGE-CONTROLLED MULTIVIBRATORM04324M04024(8) MOTOROLADUAL VOLTAGE-CONTROLLED MULTIVIBRATORThe MC4324/4024 consists of two indepe ..
MC4344L ,Phase-frequency detectorLOGIC DIAGRAMPhaseFrequencyDetector#1 . 2AmplifierPhase CD 12FrequencyDetector 9#2 . 6Vcc-- Pin 14G ..
MC44002P ,CHROMA 4 VIDEO PROCESSORELECTRICAL CHARACTERISTICS (V = 5.0 Vdc, I = 70 μA, T = 25°C, unless otherwise noted.)CC 3 ACharac ..
MC44002P ,CHROMA 4 VIDEO PROCESSORfeatures include 4 selectable matrix modes (primarily forNTSC), fast beam current limiting and 16:9 ..
MC44007P ,CHROMA 4 VIDEO PROCESSORMAXIMUM RATINGS (T = 25°C, unless otherwise noted.)A 1 15 26 B-Y InputsRating Pin Symbol Value Unit ..
MC10H334
Quad Bus Driver/Receiver Translator
-----The MC10H334 is a Quad Bus Driver/Receiver with transmit and
receiver latches. When disabled, (OE = high) the bus outputs will fall
to –2.0 V. Data to be transmitted or received is passed through its
respective latch when the respective latch enable (DLE and RLE) is at
a low level. Information is latched on the positive transition of DLE
and RLE. The parameters specified are with 25 Ω loading on the bus
drivers and 50 Ω loads on the receivers. Propagation Delay, 1.6 ns Typical Data–to–Output Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
DIP & PLCC
PIN ASSIGNMENTVCC
BUS1
BUS0
VCC02
DLE
VCC03
BUS2
BUS3
RLE
VEE
VCC02
NOTE:Each MECL 10H series circuit has been designed
to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than
500 Ifpm is maintained. Receiver outputs are
terminated through a 50–ohm resistor to –2.0 volts
dc. Bus outputs are terminated through a 25–ohm
resistor to –2.0 volts dc.
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–20
L SUFFIX
CASE 732
PDIP–20
P SUFFIX
CASE 738
PLCC–20
FN SUFFIX
CASE 775
