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MC10H135LMOT?N/a2000avaiDual J-K Master-Slave Flip-Flop
MC10H135PMOTN/a300avaiDual J-K Master-Slave Flip-Flop


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MC10H135L-MC10H135P
Dual J-K Master-Slave Flip-Flop
SEMICONDUCTOR TECHNICAL DATA -
The MC10H135 is a dual J–K master–slave flip–flop. The device is provided
with an asynchronous set(s) and reset(R). These set and reset inputs overide
the clock.
A common clock is provided with separate J–K inputs. When the clock is
static, the JK inputs do not effect the output. The output states of the flip flop
change on the positive transition of the clock. Propagation delay, 1.5 ns Typical • Improved Noise Margin 150 Power Dissipation, 280 mW mV (Over Operating Voltage
Typical/Pkg. (No Load) and Temperature Range) ftog 250 MHz Max• Voltage Compensated MECL 10K–Compatible
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
AC PARAMETERS
NOTE:

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
DIP PIN ASSIGNMENT

VCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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