MC10H131FNR2 ,Dual Type D Master-Slave Flip-FlopELECTRICAL CHARACTERISTICS (V = –5.2 V ±5%) (See Note 1.)EE0° 25° 75°Symbol Characteristic Min Max ..
MC10H131FNR2 ,Dual Type D Master-Slave Flip-Flopfeatures of an ECL device make itrequirement stems only from the speed performance aspectideal for ..
MC10H131FNR2 ,Dual Type D Master-Slave Flip-Flop
MC10H131FNR2 ,Dual Type D Master-Slave Flip-Flop
MC10H131FNR2G , Dual D Type Master−Slave Flip−Flop
MC10H131L ,Dual D Type Master-Slave Flip-FlopMAXIMUM RATINGSCharacteristic Symbol Rating UnitPower Supply (V = 0) V –8.0 to 0 VdcCC EE
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MC34268D ,800mA, 2.85, SCSI-2 Active Terminator, Low Dropout Voltage Regulator2V -V , DROPOUT VOLTAGE (V)in OI , OUTPUT CURRENTOΔ V , OUTPUT VOLTAGE DEVIATIONOMC34268V MC34268 V ..
MC34268DR2 ,800mA, 2.85, SCSI-2 Active Terminator, Low Dropout Voltage Regulatorfeatures include current a requirement. Also, the capacitance and ESR of a tantalumand thermal limi ..
MC34268DR2 ,800mA, 2.85, SCSI-2 Active Terminator, Low Dropout Voltage RegulatorELECTRICAL CHARACTERISTICS(V = 4.25 V, C = 10 F, for typical values T = 25°C, for min/max values T ..
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MC34268DTRK ,800mA, 2.85, SCSI-2 Active Terminator, Low Dropout Voltage Regulatorcircuits. This device offers the circuit designer an economicalMARKINGsolution for precision voltag ..
MC10H131FNR2
Dual Type D Master-Slave Flip-Flop
---The MC10H131 is a MECL 10H part which is a functional/pinout
duplication of the standard MECL 10K family part, with 100%
improvement in clock speed and propagation delay and no increase in
power–supply current. Propagation Delay, 1.0 ns Typical Power Dissipation, 235 mW Typical Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENTVCC1
CE1
VEE
VCC2
CE2
VCC1 = PIN 1
VCC2 = PIN 16
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE2 11
D2 10
S2 12
CLOCKED TRUTH TABLEN.D. = Not Defined
C = CE + CC
A clock H is a clock transition
from a low to a high state.
RS TRUTH TABLEPin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
http://
ORDERING INFORMATION
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
