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MC10H123LN/a6avaiTriple 4-3-3-Input Bus Driver
MC10H123PMOT ?N/a13avaiTriple 4-3-3-Input Bus Driver


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MC10H123L-MC10H123P
Triple 4-3-3-Input Bus Driver
SEMICONDUCTOR TECHNICAL DATA -
The MC10H123 is a triple 4–3–3–Input Bus Driver.
The MC10H123 consists of three NOR gates designed for bus driving
applications on card or between cards. Output low logic levels are specified with
VOL = –2.1 Vdc so that the bus may be terminated to –2.0 Vdc. The gate output,
when low, appears as a high impedance to the bus, because the output
emitter–followers of the MC10H123 are “turned–off.” This eliminates
discontinuities in the characteristic impedance of the bus.
The VOH level is specified when driving a 25–ohm load terminated to –2.0
Vdc, the equivalent of a 50–ohm bus terminated at both ends. Although 25
ohms is the lowest characteristic impedance that can be driven by the
MC10H123, higher impedance values may be used with this part. A typical
50–ohm bus is shown in Figure 1. Propagation Delay, 1.5 ns Typical Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
AC PARAMETERS
NOTE:

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.1 volts.
DIP
PIN ASSIGNMENT

VCC1
BOUT
AOUT
AIN
AIN
AIN
AIN
VEE
VCC2
COUT
CIN
CIN
CIN
BIN
BIN
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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