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MC10H113ON ?N/a98avaiQuad XOR Gate


MC10H113 ,Quad XOR Gate2MC10H113PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
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MC10H113
Quad XOR Gate
---The MC10H113 is a Quad Exclusive OR Gate with an enable
common to all four gates. The outputs may be wire–ORed together to
perform a 4–bit comparison function (A = B). The enable is active
LOW. Propagation Delay, 1.3 ns Typical Power Dissipation 175 mW Typ/Pkg (No Load) Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT

VCC1
AOUT
BOUT
AIN
AIN
BIN
BIN
VEE
VCC2
DOUT
COUT
DIN
DIN
CIN
CIN
ENABLE9
TRUTH TABLE
15
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 14 3 2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS
= Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775

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