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MC10ELT21D
Differential PECL to TTL Translator
SEMICONDUCTOR TECHNICAL DATA --
The MC10ELT/100ELT21 is a differential PECL to TTL translator.
Because PECL (Positive ECL) levels are used only +5V and ground are
required. The small outline 8-lead SOIC package and the single gate of
the ELT21 makes it ideal for those applications where space,
performance and low power are at a premium. Because the mature
MOSAIC 1.5 process is used, low cost can be added to the list of
features.
The VBB output allows the ELT21 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the IN input for a
non-inverting buffer or the IN input for an inverting buffer. If used the VBB
pin should be bypassed to ground via a 0.01μF capacitor.
The ELT21 is available in both ECL standards: the 10ELT is compatible
with positive MECL 10H logic levels while the 100ELT is compatible with
positive ECL 100K logic levels. 3.5ns Typical Propagation Delay Differential PECL Inputs Small Outline SOIC Package 24mA TTL Output Flow Through Pinouts
GND
VCC
LOGIC DIAGRAM AND PINOUT ASSIGNMENTD0
VBB
