MC10176P ,Hex D Master/Slave Flip-FlopELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10178L ,Binary CounterLOGIC DIAGRAMCASE 648–08FN SUFFIXS0 Q0 S1 Q1 S2 Q2 S3 Q3PLCC11 15 7 13 6 4 5 2CASE 775–02S S S SD1 ..
MC10178P ,Binary CounterLOGIC DIAGRAMCASE 648–08FN SUFFIXS0 Q0 S1 Q1 S2 Q2 S3 Q3PLCC11 15 7 13 6 4 5 2CASE 775–02S S S SD1 ..
MC10181L ,4-Bit Arithmetic Logic Unit/Function GeneratorLOGIC DIAGRAMV V1 24CC1 CC21315 F0 M2 23V = PIN 1CC117V = PIN 24 14 CC2F1 3 22 CNV = PIN 12EES0 S1 ..
MC10186FN ,Hex D Master-Slave Flip-Flop With Reset**SEMICONDUCTOR TECHNICAL DATA * * The MC10186 contains six high–speed, master slave type “D” flip ..
MC10186L ,Hex D Master-Slave Flip-Flop With ResetLOGIC DIAGRAMDIPPIN ASSIGNMENTD0 5 2 Q0RESET 1 16 VCCQ0 2 15 Q5D1 6 3 Q1 Q1 Q43 14Q2 Q34 13D5D0 5 1 ..
MC3361BD ,LOW POWER NARROWBAND FM IFOrder this document by MC3361B/D* ** * ** **The MC3361B includes an Oscillator, Mixer, Limiting Am ..
MC3361BP ,Low voltage/power narrow band FM IF. Operating voltage: 2.5-7.0V. Operating current: 4.0mA(squelch off V12=2V), 6.0mA(squelch on V12=GND).Maximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MC3361BPG-S16-R , LOW VOLTAGE/POWER NARROW BAND FM IF
MC3361BPL-S16-R , LOW VOLTAGE/POWER NARROW BAND FM IF
MC3361CD ,LOW POWER NARROWBAND FM IFMAXIMUM RATINGS (T A = 25°C, unless otherwise noted.)Rating Pln Symbol Value UnitPower Supply Volta ..
MC3361CDR2 ,V(dc): 10V; ; low power narrowband FM IFOrder this document by MC3361C/D**The MC3361C includes an Oscillator, Mixer, Limiting Amplifier,Qua ..
MC10176L-MC10176P
Hex D Master/Slave Flip-Flop
SEMICONDUCTOR TECHNICAL DATA -
The MC10176 contains six high-speed, master slave type “D” flip-flops.
Clocking is common to all six flip-flops. Data is entered into the master when the
clock is low. Master to slave data transfer takes place on the positive-going
Clock transition. Thus, outputs may change only on a positive-going Clock
transition. A change in the information present at the data (D) input will not affect
the output information any other time due to the master-slave construction of
this device. = 460 mW typ/pkg (No Load)
ftoggle= 150 MHz (typ)
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 5
CLOCK9
Q0
3 Q1
4 Q2 Q3 Q4 Q5D1D2D3D4 12
CLOCKED TRUTH TABLE*A clock H is a clock transition
from a low to a high state.
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
CLOCK
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
