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MC10141LMOT?N/a2000avaiFour Bit Universal Shift Register
MC10141L. |MC10141LAMI ?N/a15avaiFour Bit Universal Shift Register
MC10141PMOTON/a229avaiFour Bit Universal Shift Register


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MC10141L-MC10141L.-MC10141P
Four Bit Universal Shift Register
SEMICONDUCTOR TECHNICAL DATA -
The MC10141 is a four–bit universal shift register which performs shift left, or
shift right, serial/parallel in, and serial/parallel out operations with no external
gating. Inputs S1 and S2 control the four possible operations of the register
without external gating of the clock. The flip–flops shift information on the
positive edge of the clock. The four operations are stop shift, shift left, shift right,
and parallel entry of data. The other six inputs are all data type inputs; four for
parallel entry data, and one for shifting in from the left (DL) and one for shifting
in from the right (DR).= 425 mW typ/pkg (No Load)
fShift= 200 MHz typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM

VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 D1 D0 Q1 Q0
TRUTH TABLE

*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
DIP
PIN ASSIGNMENT

VCC1
VEE
VCC2
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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