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MC10138LMOT?N/a2000avaiBi-Quinary Counter
MC10138PMOTOROLA N/a25avaiBi-Quinary Counter
MC10138PMOTN/a200avaiBi-Quinary Counter


MC10138L ,Bi-Quinary CounterLOGIC DIAGRAM PLASTIC PACKAGECASE 648–08S0 Q0 S1 Q1 S2 Q2 S3 Q311 15 10 13 6 4 5 2FN SUFFIXPLCCCASE ..
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MC10138L-MC10138P
Bi-Quinary Counter
SEMICONDUCTOR TECHNICAL DATA-
The MC10138 is a four bit counter capable of divide by two, five, or ten
functions. It is composed of four set–reset master–slave flip–flops. Clock
inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or
“clear.” Individual set and common reset inputs are provided, as well as
complementary outputs for the first and fourth bits. = 370 mW typ/pkg (No Load)
ftog = 150 MHz typ
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAM

VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8 Q014
Clock
Reset Q17 Q2 Q33
COUNTER TRUTH TABLES
BI–QUINARY

(Clock connected to C2
and Q3 connected to C1)
BCD

(Clock connected to C1
and Q0 connected to C2)
COUNTER STATE DIAGRAM — POSITIVE LOGIC
7112 2 3 4
CLOCK CONNECTED TO C2 Q0 CONNECTED TO C2
DIP
PIN ASSIGNMENT

VCC1
VEE
VCC2
RESET
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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