MC10134L ,Dual Multiplexer With LatchLOGIC DIAGRAMV V1 16CC1 CC2A0 6Q1 Q22 15A1 11D11 4 Q1 Q23 142Q1D11 D214 13D12 5D12 D225 12CEO 103Q1 ..
MC10134P ,Dual Multiplexer With Latch**SEMICONDUCTOR TECHNICAL DATA* ** * The MC10134 is a dual multiplexer with clocked D type latches. ..
MC10135L ,Dual J-K Master-Slave Flip-FlopELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10136 ,Universal Hexadecimal CounterELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10136L ,Universal Hexadecimal CounterLOGIC DIAGRAMS1 9S2 7Carry In10V = PIN 1CC1V = PIN 16CC2TV = PIN 8Q0 T Q1 T Q2 Q3 EETT TTQ0 Q1 ..
MC10136P ,Universal Hexadecimal CounterELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC33375D-2.5 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlMC33375300 mA, Low DropoutVoltage Regulator withOn/Off ControlThe MC33375 series are micropower low ..
MC33375D-3.0 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off Controlpackages, SOT−223, and SOP−8 surface mount packages. Thesedevices feature a very low quiescent curr ..
MC33375D-3.0R2 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlELECTRICAL CHARACTERISTICS (C = 1.0μF, T = 25°C, for min/max values T = −40°C to +125°C, Note 1)L A ..
MC33375D-3.3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlFeatures:12 3• Low Quiescent Current (0.3 A in OFF mode; 125 A in ON mode)V ON/OFF Vin out• Low I ..
MC33375D-3.3R2G , 300 mA, Low Dropout Voltage Regulator with On/Off Control
MC33375ST-1.8T3 ,300mA, 5V, Low Dropout Voltage Regulator with On/Off ControlELECTRICAL CHARACTERISTICS (C = 1.0μF, T = 25°C, for min/max values T = −40°C to +125°C, Note 1)L A ..
MC10134L-MC10134P
Dual Multiplexer With Latch
SEMICONDUCTOR TECHNICAL DATA -
The MC10134 is a dual multiplexer with clocked D type latches. Each latch
may be clocked separately by holding the common clock in the low state, and
using the clock enable inputs for the clocking function. If the common clock is to
be used to clock the latch, the clock enable (CE) inputs must be in the low state.
In this mode, the enable inputs perform the function of controlling the common
clock (CC).
The data select inputs determine which data input is enabled. A high (H)
level on the A0 input enables data input D12 and a low (L) level on the A0 input
enables data input D11. A high (H) level on the A1 input enables data input D22
and a low (L) level on the A1 input enables data input D21.
Any change on the data input will be reflected at the outputs while the clock is
low. The outputs are latched on the positive transition of the clock. While the
clock is in the high state, a change in the information present at the data inputs
will not affect the output information. = 225 mW typ/pkg (No Load)
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8A1
2Q14D11D12CEOCCCE1D21D22
3Q1Q2Q2A0
TRUTH TABLEC = CE + CC
DIP
PIN ASSIGNMENTVCC1
D11
D12
VEE
VCC2
D21
D22
CEO
CE1
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
