MC100LVEP34DTR2G ,2.5V / 3.3V ECL /2, /4, /8 Clock Generation ChipBBgenerated voltage supply, is available to this device only. Forsingle−ended input conditions, the ..
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MC100LVEP34DTR2G
2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip
MC100LVEP34
2.5V / 3.3V�ECL ÷2, ÷4, ÷8
Clock Generation Chip
The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single−ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 �F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal dividerstages. The internal enable flip−flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start−up, the internal flip−flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEP34s in a system. Single−ended CLK
input operation is limited to a VCC ≥ 3.0 V in PECL mode, or VEE ≤
−3.0 V in NECL mode. 35 ps Output−to−Output Skew Synchronous Enable/Disable Master Reset for Synchronization The 100 Series Contains Temperature Compensation. PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V Open Input Default State LVDS Input Compatible Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.
