MC100LVEL51DTR2 ,3.3V ECL Differential Clock D Flip-Flop2MC100LVEL51LVPECL DC CHARACTERISTICS V = 3.3 V; V = 0.0 V (Note 1)CC EE–40°C 25°C 85°CSymbol Chara ..
MC100LVEL56 ,3.3V ECL Dual Differential 2:1 Multiplexer
MC100LVEL56 ,3.3V ECL Dual Differential 2:1 Multiplexer
MC100LVEL56 ,3.3V ECL Dual Differential 2:1 Multiplexerfeatures both individual and common select inputs toaddress both data path and random logic applica ..
mc100LVEL56DW ,3.3V ECL Dual Differential 2:1 MultiplexerAN1672/DThe ECL Translator GuidePECL • LVPECL • NECL • TTL •LVTTL/LVCMOS • CMOS
MC100LVEL56DWR2 ,3.3V ECL Dual Differential 2:1 MultiplexerPrepared by: Paul ShockmanON SemiconductorAPPLICATION NOTEObjectiveGeneral BackgroundThis applicati ..
MC33192DW ,MI-BUS INTERFACE STEPPER MOTOR CONTROLLERGeneral Descriptionto control two phase bipolar stepper motors operated in eitherThe Motorola Inter ..
MC33197AP ,AUTOMOTIVE WASH WIPER TIMEROrder this document by MC33197A/D * ** **AUTOMOTIVE WASHThe MC33197A is a standard wiper timer co ..
MC33198 ,High Side TMOS Driver
MC33198 ,High Side TMOS Driver
MC33198D ,Automotive High Side TMOS DriverELECTRICAL CHARACTERISTICS.Tamb from - 40 °C to +125 °C, Vcc from 7V to 20V, unless otherwise note. ..
MC33199D ,ISO 9141 SERIAL LINK DRIVERELECTRICAL CHARACTERISTICS (continued) (– 40°C ≤ T ≤ 125°C, 4.5 V ≤ V ≤ 5.5 V, 4.5 V ≤ V ≤ 20 V, un ..
MC100LVEL51DTR2
3.3V ECL Differential Clock D Flip-Flop
MC100LVEL51
3.3V�ECL Differential Clock
D Flip�Flop
The MC100LVEL51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the EL51 device, but operates from a
3.3 V supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3 V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the L VEL51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability
under open input conditions. When left open, the CLK input will be
pulled down to VEE and the CLK input will be biased at VCC/2. 475 ps Propagation Delay 2.8 GHz Toggle Frequency ESD Protection: >4 KV HBM, >200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC= 3.0 V to 3.8 V
with VEE= 0 V NECL Mode Operating Range: VCC= 0 V
with VEE= –3.0 V to –3.8 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34 Transistor Count = 114 devices
