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MC100E112FNR2MOTN/a172avai5V ECL Quad Driver
MC100E136FNMN/a39avai6-BIT UNIVERSAL UP/DOWN COUNTER
MC100E164FNONN/a83avai5V ECL 16:1 Multiplexer
MC100E166FNONN/a16avai9-BIT MAGNITUDE COMPARATOR
MC100EL15DR2ONN/a7290avai5V ECL 1:4 Clock Distribution Chip
MC100EP016AonN/a288avai3.3V / 5V ECL 8-Bit Synchronous Binary Up Counter
MC100EP01DR2ON SemiconductorN/a5000avai3.3V / 5V ECL 4-Input OR/NOR
MC100EP210SONN/a18avai2.5V 1:5 Dual Differential LVDS Clock Driver
MC100EP809FAONN/a17avai3.3 V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
MC100EPT24DONN/a2229avai3.3V LVTTL/LVCMOS to Differential LVECL Translator
MC100EPT24DMOTN/a96avai3.3V LVTTL/LVCMOS to Differential LVECL Translator
MC100H600MOTORMLN/a11avai9-Bit TTL-ECL Translator
MC100H641MOTOROLAN/a260avai1:9 Clock Driver
MC100LVE164N/a120avai3.3V ECL 16:1 Multiplexer
MC100LVE210FNR2ONN/a456avai3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer
MC100LVEL01DTR2ONN/a2500avai3.3V ECL 4-Input OR/NOR
MC100LVEL30DWONN/a20avai3.3V ECL Triple D-Type Flip-Flop with Set and Reset
MC100LVEL31DTR2ONN/a17436avai3.3V ECL D-Type Flip-Flop with Set and Reset
MC100LVELT22DONN/a720avai3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100LVELT23DTONN/a570avai3.3V Dual Differential LVPECL to LVTTL Translator
MC100LVEP11DONN/a2506avai2.5V / 3.3V ECL 1:2 Differential Fanout Buffer
MC10E136FNR2MOTON/a1000avai5V ECL 6-Bit Universal Up/Down Counter
MC10E136FNR2MOTN/a484avai5V ECL 6-Bit Universal Up/Down Counter
MC10E157FNR2ONN/a1000avai5V ECL Quad 2:1 Multiplexer
MC10E404FNONN/a293avai5V ECL Quad Differential AND/NAND
MC10E416FNONN/a36avai5V ECL Quint Differential Line Receiver
MC10EL05DR2ONN/a5000avai5V ECL 2-Input Differential AND/NAND
MC10EL31DN/a14avai5V ECL D-Type Flip-Flop with Set and Reset
MC10EP01DR2ONN/a2500avai3.3V / 5V ECL 4-Input OR/NOR
MC10EP01DTR2ONN/a4800avai3.3V / 5V ECL 4-Input OR/NOR
MC10EP16TDN/a200avai3.3V / 5V ECL Differential Receiver/Driver
MC10EP33DTONN/a30avai3.3V / 5V ECL Divide By 4 Divider
MC10EP52DMOTN/a306avai3.3V / 5V ECL Differential Data and Clock D Flip Flop
MC10H107MELMOTORMLN/a250avaiTriple 2-Input XOR/XNOR Gate
MC10H109MELONN/a2530avaiDual 4-5-Input OR/NOR Gate
MC10H113MELMOTN/a900avaiQuad XOR Gate
MC10H113MELMOTOROLA ?N/a6252avaiQuad XOR Gate
MC10H117FNR2ONN/a1000avaiDual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
MC10H186FNONN/a63avaiHex D Master-Slave Flip-Flop with Reset
MC10H211FNR2ONN/a3500avaiDual 3-Input 3-Output NOR Gate
MC10H211FNR2MOTN/a1000avaiDual 3-Input 3-Output NOR Gate
MC10H351MONN/a140avaiTTL, NMOS To ECL Translator
MC10H603FNONN/a13avai9-Bit Latch/ECL-TTL Translator


MC100LVEL31DTR2 ,3.3V ECL D-Type Flip-Flop with Set and Reset
MC100LVEL32D ,3.3V ECL ÷2 Dividerhttp://onsemi.com3ECLSOIC8EVBEvaluation Board Assembly Instructions On the top side of the evaluati ..
MC100LVEL32DG , 3.3V ECL ÷2 Divider
MC100LVEL32DG , 3.3V ECL ÷2 Divider
MC100LVEL32DR2G , 3.3V ECL ÷2 Divider
MC100LVEL32DR2G , 3.3V ECL ÷2 Divider
MC33179DG , Low Power, Low Noise Operational Amplifiers
MC33179DR2 ,Low Power, Low Noise Quad Operational AmplifierMC33178, MC33179Low Power, Low NoiseOperational AmplifiersThe MC33178/9 series is a family of high ..
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179DTBR2G , Low Power, Low Noise Operational Amplifiers
MC33179P ,HIGH OUTPUT CURRENT LOW POWER, LOW NOISE OPERATIONAL AMPLIFIERSOrder this document by MC33178/D** * ** * * * ** * * *HIGH OUTPUT CURRENTThe MC33178/9 series i ..


MC100E112FNR2-MC100E136FN-MC100E164FN-MC100E166FN-MC100EL15DR2-MC100EP016A-MC100EP01DR2-MC100EP210S-MC100EP809FA-MC100EPT24D-MC100H600-MC100H641-MC100LVE164-MC100LVE210FNR2-MC100LVEL01DTR2-MC100LVEL30DW-MC100LVEL31DTR2-MC100LVELT22D-MC100LVELT23DT-MC100LVEP11D-
Hex Buffer with Enable
AND8066/D
Interfacing with ECLinPS
Prepared by: Paul Shockman

ON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVER

A typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at VCC power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as Vpp and
VIHCMR. When an input is interconnected as a differential
signal, the DC Single Ended parameters of VIL and VIH do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
VCC
VTT
VCC
Figure 1. Standard Differential ECL Interconnect
SINGLE–ENDED INTERFACE

Signals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
VCC
Figure 2. Standard Single–Ended ECL Interconnect

VTT
VCC
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as VIH and VIL
Parameters. Each temperature has a minimum and
maximum limit pair to VIH and VIL parameters, thus
defining the Single–Ended input swing, Vpp(SE). The
Vpp(SE) ranges from 595 mV to 890 mV , depending on the
temperature and family. The Vpp(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
Figure 3. Differential Driver with Independent
Standard Single–Ended Receivers

VTT
VCC
VEE
VTT
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