MC100LVE310 ,3.3V ECL 2:8 Differential Fanout Bufferhttp://onsemi.com2MC100LVE310LVPECL DC CHARACTERISTICS V = 3.3 V; V = 0.0 V (Note 1)CC EE–40°C 25°C ..
MC100LVE310FN ,3.3V ECL 2:8 Differential Fanout Bufferhttp://onsemi.comsystem skew. The LVE310 offers two selectable clock inputs to allowfor redundant o ..
MC100LVE310FNG , 3.3V ECL 2:8 Differential Fanout Buffer
MC100LVEL01DT ,3.3V ECL 4-Input OR/NORECLSOIC8EVBEvaluation Board Manualfor High Frequency SOIC 8
MC100LVEL01DTR2 ,3.3V ECL 4-Input OR/NOR
MC100LVEL05 ,4-input differential AND/NANDPrepared byCleon PettyAPPLICATION NOTETodd PearsonECL Applications EngineeringThis application note ..
MC33171DT ,LOW POWER SINGLE BIPOLAR OP-AMPSMC33171 - MC35171LOW POWERSINGLE BIPOLAR OPERATIONAL AMPLIFIERS ■ GOOD CONSUMPTION/SPEED RATIO : ..
MC33171N ,LOW POWER SINGLE BIPOLAR OP-AMPSMC33171 - MC35171LOW POWERSINGLE BIPOLAR OPERATIONAL AMPLIFIERS ■ GOOD CONSUMPTION/SPEED RATIO : ..
MC33171P ,Low Power, Single Supply Operational AmplifiersOrder this document by MC33171/D * ** ** *DUALQuality bipolar fabrication with innovative design c ..
MC33172 ,LOW POWER DUAL BIPOLAR OP-AMPSMC33172 - MC35172LOW POWERDUAL BIPOLAR OPERATIONAL AMPLIFIERS ■ GOOD CONSUMPTION/SPEED RATIO : ..
MC33172D ,LOW POWER DUAL BIPOLAR OP-AMPSOrder this document by MC33171/D * ** ** *DUALQuality bipolar fabrication with innovative design c ..
MC33172DG ,Single Supply 3V to 44V, Low Power Dual Op Amphttp://onsemi.comQuality bipolar fabrication with innovative design concepts areemployed for the MC ..
MC100LVE310-MC100LVE310FN
3.3V ECL 2:8 Differential Fanout Buffer
MC100LVE310
3.3V�ECL 2:8 Differential
Fanout Buffer
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and
system skew. The LVE310 offers two selectable clock inputs to allow
for redundant or test clocks to be incorporated into the system clock
trees.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 Ω, even if
only one side is being used. In most applications all eight differential
pairs will be used and therefore terminated. In the case where fewer
than eight pairs are used it is necessary to terminate at least the output
pairs adjacent to the output pair being used in order to maintain
minimum skew. Failure to follow this guideline will result in small
degradations of propagation delay (on the order of 10–20 ps) of the
outputs being used, while not catastrophic to most designs this will
result in an increase in skew. Note that the package corners isolate
outputs from one another such that the guideline expressed above
holds only for outputs on the same side of the package.
The MC100LVE310, as with most ECL devices, can be operated
from a positive VCC supply in LVPECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE310’s performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment series or Thevenin line terminations are typically
used as they require no additional power supplies, if parallel
termination is desired a terminating voltage of VCC–2.0 V will need to
be provided. For more information on using PECL, designers should
refer to Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open. 200 ps Part–to–Part Skew 50 ps Output–to–Output Skew The 100 Series Contains Temperature Compensation ESD Protection: >2 KV HBM, >200 V MM PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V NECL Mode Operating Range:VCC= 0 V with VEE= –3.0 V to –3.8 V Internal Input Pulldown Resistors Q Output will Default LOW with All Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
ORDERING INFORMATION
MARKING DIAGRAM = Assembly Location = Wafer Lot = Year = Work Week
PLCC–28
FN SUFFIX
CASE 776http://
