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MC100EL33DR2MOTN/a121avai5V ECL Divide by 4 Divider


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MC100EL33DR2
5V ECL Divide by 4 Divider
MC10EL33, MC100EL33
5V�ECL ÷4 Divider
The MC10EL/100EL33 is an integrated ÷4 divider. The differential
clock inputs and the VBB allow a differential, single-ended or AC coupled
interface to the device. The VBB pin, an internally generated voltage
supply, is available to this device only. For single-ended input conditions,
the unused differential input is connected to VBB as a switching reference
voltage. VBB may also rebias AC coupled inputs. When used, decouple
VBB and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge. Upon
power-up, the internal flip-flops will attain a random state; the reset allows
for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation. 650 ps Propagation Delay 4.0 GHz Toggle Frequency ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 100 V PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input Pulldown Resistors on CLK(s) and R. Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34 Transistor Count = 95 devices
Figure 1. Logic Diagram and Pinout Assignment

VEE
VCCCLK
VBB
Reset
CLK
Table 1. PIN DESCRIPTION
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