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MC100E451FNONN/a11avai5V ECL 6-Bit D Register Differential Data and Clock


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MC100E451FN
5V ECL 6-Bit D Register Differential Data and Clock
MC10E451, MC100E451
5V�ECL 6-Bit D Register
Differential Data and Clock
The MC10E/100E451 contains six D−type flip−flops with
single−ended outputs and differential data inputs. The common clock
input is also differential. The registers are triggered by a positive
transition of the positive clock (CLK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to
LOW.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of
the inputs. Because of the edge triggered flip−flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the
input clamps only operate when both inputs fall to 2.5 V below VCC.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 �F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation. Differential Inputs: Data and Clock VBB Output 1100 MHz Min. Toggle Frequency Asynchronous Master Reset PECL Mode Operating Range:
VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range:
VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 k� Pulldown Resistors ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34 Transistor Count = 348 devices
MARKING
DIAGRAMS
= Assembly Location = Wafer Lot = Year = Work Week
PLCC−28
FN SUFFIX
CASE 776

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