MAXQ610A-2524+T ,16-Bit Microcontroller with Infrared ModuleFeatures16-bit RISC microcontroller and integrated peripheralsincluding two USARTs and an SPI™ mast ..
MAXQ610A-2541+T ,16-Bit Microcontroller with Infrared ModuleBlock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MAXQ610J-0000+ ,16-Bit Microcontroller with Infrared ModuleFeatures†MAXQ610J-0000+ 0°C to +70°C 44 TQFN-EP♦ High-Performance, Low-Power 16-Bit RISC CoreMAXQ61 ..
MAXQ610J-2519+ ,16-Bit Microcontroller with Infrared Moduleapplications toexecute on the MAXQ610, while limiting access to onlyModulationdata and code allowed ..
MAXQ610J-2519+T ,16-Bit Microcontroller with Infrared ModuleTABLE OF CONTENTSAbsolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MAXQ610J-2903+T ,16-Bit Microcontroller with Infrared Moduleapplications includ-♦ Secure MMU for Application Partitioning and IPing universal remote controls, ..
MB89F202P-SH ,8-Bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12561-1EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89202 S ..
MB89F499PFV , 8-bit Proprietary Microcontroller CMOS
MB89F538 , 8-bit Original Microcontroller CMOS, F-2MC-8L MB89530A Series
MB89F538-101PFM , 8-bit Original Microcontroller CMOS, F-2MC-8L MB89530A Series
MB89F538L ,F2MC-8L/Low Power/Low Voltage MicrocontrollersFUJITSU SEMICONDUCTORDS07-12548-3EDATA SHEET8-bit Original Microcontroller CMOS2F MC-8L MB89530 Ser ..
MB89P131-101 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12509-6EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89120/1 ..
MAXQ610A-2524+-MAXQ610A-2524+T-MAXQ610A-2541+T-MAXQ610J-0000+-MAXQ610J-2519+-MAXQ610J-2519+T-MAXQ610J-2903+T-MAXQ610J-UEI+
16-Bit Microcontroller with Infrared Module
General DescriptionThe MAXQ610 is a low-power, 16-bit MAXQ®micro-
controller designed for low-power applications includ-
ing universal remote controls, consumer electronics,
and white goods. The MAXQ610 combines a powerful
16-bit RISC microcontroller and integrated peripherals
including two USARTs and an SPI™ master/slave com-
munications port, along with an IR module with carrier
frequency generation and flexible port I/O capable of
multiplexed keypad control.
The MAXQ610 includes 64KB of flash memory and 2KB
of data SRAM. Intellectual property (IP) protection is
provided by a secure MMU that supports multiple
application privilege levels and protects code against
copying and reverse engineering. Privilege levels
enable vendors to provide libraries and applications to
execute on the MAXQ610, while limiting access to only
data and code allowed by their privilege level.
For the ultimate in low-power battery-operated perfor-
mance, the MAXQ610 includes an ultra-low-power stop
mode (0.2µA, typ). In this mode, the minimum amount
of circuitry is powered. Wake-up sources include exter-
nal interrupts, the power-fail interrupt, and a timer inter-
rupt. The microcontroller runs from a wide 1.70V to 3.6V
operating voltage.
ApplicationsRemote Controls
Battery-Powered Portable Equipment
Consumer Electronics
Home Appliances
White Goods
FeaturesHigh-Performance, Low-Power 16-Bit RISC CoreDC to 12MHz Operation Across Entire Operating
Range1.70V to 3.6V Operating Voltage Range33 Total Instructions for Simplified ProgrammingThree Independent Data Pointers Accelerate Data
Movement with Automatic Increment/DecrementDedicated Pointer for Direct Read from Code Space16-Bit Instruction Word, 16-Bit Data Bus16 x 16-Bit General-Purpose Working RegistersSecure MMU for Application Partitioning and IP
ProtectionMemory Features64KB Flash:
512 Byte Sectors
20,000 Erase/Write Cycles per Sector
Masked ROM Available
2KB Data SRAM
Additional PeripheralsPower-Fail Warning
Power-On Reset/Brownout Reset
Automatic IR Carrier Frequency Generation and
Modulation
Two 16-Bit, Programmable Timers/Counters with
Prescaler and Capture/Compare
SPI and Two USART Communication Ports
Programmable Watchdog Timer
8kHz Nanopower Ring Oscillator Wake-Up Timer
Up to 24 (MAXQ610A) or 32 (MAXQ610B)
General-Purpose I/Os
Low-Power Consumption0.2µA (typ), 2.0µA (max) in Stop Mode= +25°C, Power-Fail Monitor Disabled
3.75mA (typ) at 12MHz in Active Mode
MAXQ610
16-Bit Microcontroller with Infrared Module
Ordering Information19-4715; Rev 6; 7/11
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
EVALUATION KIT
AVAILABLE
Note:The 4-digit suffix “-0000” indicates a microcontroller in the
default state with the flash memory unprogrammed. Any value
other than 0000 indicates a device preprogrammed at Maxim
with proprietary customer-supplied software. For more information
on factory preprogramming of these devices, contact Maxim at
https://support.maxim-ic.com/micro. Information on maskedROM devices and tape and reel versions are also available.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Contact factory for ordering requirements.
†EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE MAXQ610A-0000+ 0°C to +70°C 32 TQFN-EP†
MAXQ610B-0000+ 0°C to +70°C 40 TQFN-EP†
MAXQ610J-0000+ 0°C to +70°C 44 TQFN-EP†
MAXQ610X-0000+* 0°C to +70°C Bare die
Pin Configurations and Selector Guide appear at end of
data sheet.MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MAXQ610
16-Bit Microcontroller with Infrared ModuleAbsolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Loading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Differences for ROM Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
TABLE OF CONTENTS
MAXQ610
16-Bit Microcontroller with Infrared ModuleTable 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . .25
LIST OF TABLESFigure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 9. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 10. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 11. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
LIST OF FIGURES
MAXQ610
16-Bit Microcontroller with Infrared Module
RECOMMENDED DC OPERATING CONDITIONS(VDD= VRSTto 3.6V, TA= 0°C to +70°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDDwith Respect to GND.......-0.3V to +3.6V
Voltage Range on Any Lead with Respect
to GND except VDD......................................-0.3V to (VDD+ 0.5V)
Continuous Power Dissipation (Multilayer Board, TA= +70°C)
32 TQFN (derate 34.5mW/°C above +70°C)...........2758.6mW
40 TQFN (derate 35.7mW/°C above +70°C)..............2963mW
44 TQFN (derate 37mW/°C above +70°C)..............2758.6mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD VRST 3.6 V
1.8V Internal Regulator VREG18 1.62 1.8 1.98 V
Power-Fail Warning Voltage for
Supply (Notes 2, 3) VPFW Monitors VDD 1.75 1.8 1.85 V
Power-Fail Reset Voltage
(Note 4) VRST Monitors VDD 1.64 1.67 1.70 V
Power-On Reset Voltage VPOR Monitors VDD 1.0 1.42 V
RAM Data-Retention Voltage VDRV (Note 5) 1.0 V
Active Current (Note 6) IDD_1 Sysclk = 12MHz 3.75 5.1 mA
TA = +25°C 0.2 2.0 IS1 Power-Fail Off
TA = 0°C to +70°C 0.2 12
TA = +25°C 22 29.5 Stop-Mode Current
IS2 Power-Fail On TA = 0°C to +70°C 27.6 42
μA
Current Consumption During
Power-Fail IPFR (Notes 5, 7) [(3 x IS2) + ((PCI - 3) x
(IS1 + INANO))]/PCI μA
Power Consumption During
Power-On Reset IPOR (Note 8) 100 nA
Stop-Mode Resume Time tON 375 + 8192tHFXIN μs
Power-Fail Monitor Startup Time tPRM_ON (Note 5) 150 μs
Power-Fail Warning Detection
Time tPFW (Notes 5, 9) 10 μs
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins VIL VGND0.3 x
VDDV
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins VIH0.7 x
VDD VDD V
Input Hysteresis (Schmitt) VIHYS 300 mV
Input Low Voltage for HFXIN VIL_HFXIN VGND0.3 x
VDDV
ABSOLUTE MAXIMUM RATINGS
MAXQ610
16-Bit Microcontroller with Infrared Module
RECOMMENDED DC OPERATING CONDITIONS (continued)(VDD= VRSTto 3.6V, TA= 0°C to +70°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage for HFXIN VIH_HFXIN 0.7 x
VDD VDD V
IRRX Input Filter Pulse-Width
Reject tIRRX_R 50 ns
IRRX Input Filter Pulse-Width
Accept tIRRX_A 300 ns
VDD = 3.6V, IOL = 25mA (Note 5) 1.0
VDD = 2.35V, IOL = 10mA (Note 5) 1.0 Output Low Voltage for IRTX VOL_IRTX
VDD = 1.85V, IOL = 4.5mA 1.0
VDD = 3.6V, IOL = 11mA (Note 5) 0.4 0.5
VDD = 2.35V, IOL = 8mA (Note 5) 0.4 0.5 Output Low Voltage for RESET
and All Port Pins (Note 10) VOL
VDD = 1.85V, IOL = 4.5mA 0.4 0.5
Output High Voltage for IRTX and
All Port Pins VOH IOH = -2mA VDD -
0.5 VDD V
Input/Output Pin Capacitance for
All Port Pins CIO (Note 5) 15 pF
Input Leakage Current IL Internal pullup disabled -100 +100 nA
VDD = 3.0V, VOL = 0.4V (Note 5) 16 28 39 Input Pullup Resistor for RESET,
IRTX, IRRX, and All Port Pins RPUVDD = 2.0V, VOL = 0.4V 17 30 41 k
EXTERNAL CRYSTAL/RESONATOR Crystal/Resonator fHFXIN 1 12 MHz
Crystal/Resonator Period tHFXIN 1/fHFXIN ns
Crystal/Resonator Warmup Time tXTAL_RDY From initial oscillation 8192 x tHFXIN ms
Oscillator Feedback Resistor ROSCF (Note 5) 0.5 1.0 1.5 M
EXTERNAL CLOCK INPUT External Clock Frequency fXCLK DC 12 MHz
External Clock Period tXCLK 1/fXCLK ns
External Clock Duty Cycle tXCLK_DUTY 45 55 % fHFINSystem Clock Frequency fCKHFXOUT = GND fXCLKMHz
System Clock Period tCK 1/fCK MHz
NANOPOWER RING OSCILLATOR TA = +25°C3.0 8.0 20.0 Nanopower Ring Oscillator
Frequency fNANOTA = +25°C, VDD = POR voltage (Note 5) 1.7 2.4 kHz
Nanopower Ring Oscillator Duty
Cycle tNANO (Note 5) 40 60 %
Nanopower Ring Oscillator
Current INANOTypical at VDD = 1.64V, TA = +25°C
(Note 5) 40 400 nA
MAXQ610
16-Bit Microcontroller with Infrared Module
RECOMMENDED DC OPERATING CONDITIONS (continued)(VDD= VRSTto 3.6V, TA= 0°C to +70°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
WAKE-UP TIMER Wake-Up Timer Interval tWAKEUP 1/fNANO65,535/
fNANOs
FLASH MEMORY System Clock During Flash
Programming/Erase fFPSYSCLK 6 MHz
tME Mass erase 20 40 Flash Erase Time tERASE Page erase 20 40 ms
Flash Programming Time per
Word tPROG (Note 11) 20 100 μs
Write/Erase Cycles 20,000 Cycles
Data Retention TA = +25°C 100 Years
Carrier Frequency fIR (Note 5) fCK/2 Hz
Note 1:Specifications to 0°C are guaranteed by design and are not production tested.
Note 2:It is not recommended to write to flash memory when the supply voltage drops below the power-fail warning levels as
there is uncertainty in the duration of continuous power supply. The user application should check the status of the power-
fail warning flag before writing to flash to ensure complete write operations.
Note 3:The power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of
0.11V.
Note 4:The power-fail reset and power-on-reset (POR) detectors operate in tandem to ensure that one or both signals are active
at all times when VDD< VRST. Doing so ensures the device maintains the reset state until the minimum operating voltage is
achieved.
Note 5:Guaranteed by design and not production tested.
Note 6:Measured on the VDDpin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink
any current. Part is executing code from flash memory.
Note 7:The power-check interval (PCI) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles.
Note 8:Current consumption during POR when powering up while VDD< VPOR.
Note 9:The minimum amount of time that VDDmust be below VPFWbefore a power-fail event is detected.
Note 10:The maximum total current, IOH(max) and IOL(max), for all listed outputs combined should not exceed 32mA to satisfy
the maximum specified voltage drop. This does not include the IRTX output.
Note 11:Programming time does not include overhead associated with utility ROM interface.
MAXQ610
16-Bit Microcontroller with Infrared Module
SPI ELECTRICAL CHARACTERISTICS(VDD= VRSTto 3.6V, TA= 0°C to +70°C. AC electrical specifications are guaranteed by design and are not production tested.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI Master Operating Frequency 1/tMCK fCK/2 MHz
SPI Slave Operating Frequency 1/tSCK fCK/4 MHz
SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560 8.3 23.6ns
SCLK Output Pulse-Width
High/Low tMCH, tMCLtMCK/2 -
tSPI_RF ns
MOSI Output Hold Time After
SCLK Sample Edge tMOHtMCK/2 -
tSPI_RF ns
MOSI Output Valid to Sample
Edge tMOVtMCK/2 -
tSPI_RF ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup tMIS 25 ns
MISO Input to SCLK Sample
Edge Rise/Fall Hold tMIH 0 ns
SCLK Inactive to MOSI Inactive tMLHtMCK/2 -
tSPI_RF ns
SCLK Input Pulse-Width
High/Low tSCH, tSCL tSCK/2 ns
SSEL Active to First Shift Edge tSSE tSPI_RF ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup tSIS tSPI_RF ns
MOSI Input from SCLK Sample
Edge Transition Hold tSIH tSPI_RF ns
MISO Output Valid After SCLK
Shift Edge Transition tSOV 2tSPI_RF ns
SSEL Inactive tSSHtCK +
tSPI_RF ns
SCLK Inactive to SSEL Rising tSD tSPI_RF ns
MISO Output Disabled After
SSEL Edge Rise tSLH 2tCK +
2tSPI_RFns
MAXQ610
16-Bit Microcontroller with Infrared Module
Pin Description
PIN
32 TQFN40 TQFN44 TQFN NAMEFUNCTION
POWER PINS 15, 29 18, 38 19, 41 VDD
Supply Voltage 13, 22, 30 — 17, 20,
28, 42 GND
Ground. These pins must be directly connected to the ground plane. The 40-pin TQFN package does not have any ground pins and connects to ground through
the exposed pad.
14 17 18 REGOUT
Regulator Capacitor. This pin must be connected to ground through a 1.0μFexternal ceramic-chip capacitor. The capacitor must be placed as close to this
pin as possible. No devices other than the capacitor should be connected to
this pin.
— — — EP
Exposed Pad. For the 32-pin TQFN package, leave unconnected. For the 40-pin TQFN package, the exposed pad is internally connected to GND.
Connect to the ground plane.
For the 44-pin TQFN package, the EP has no internal connection to the device.
Leave unconnected. Not intended as an electrical connection point.
RESET PINS 28 37 40 RESET
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin
includes pullup current source and should be driven by an open-drain, external
source capable of sinking in excess of 4mA. This pin is driven low as an output
when an internal reset condition occurs.
CLOCK PINS 18 21 23 HFXIN
19 22 24 HFXOUT
High-Frequency Crystal Input. Connect external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is
the input for an external, high-frequency clock source when HFXOUT is
unconnected.
IR FUNCTION PINS 31 39 43 IRTX
IR Transmit Output. IR transmit pin capable of sinking 25mA. This pin defaults to high-impedance input with the weak pullup disabled during all forms of reset.
Software must configure this pin after release from reset to remove the high-
impedance input condition.
32 40 44 IRRX
IR Receive Input. IR receive pin. This pin defaults to high-impedance input with the weak pullup disabled during all forms of reset. Software must configure this
pin after release from reset to remove the high-impedance input condition.
MAXQ610
16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN
32 TQFN40 TQFN44 TQFN NAMEFUNCTION
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional I/O pins. All port pins default to high-impedance mode after a reset.
Software must configure these pins after release from reset to remove the high-
impedance input condition. All alternate functions must be enabled from
software.
32 TQFN40 TQFN44 TQFNPORTSPECIAL FUNCTION 1 1 1 P0.0 IRTXM
2 3 3 P0.1 RX0
3 5 5 P0.2 TX0
4 6 6 P0.3 RX1
5 7 7 P0.4 TX1
6 8 8 P0.5 TBA0/TBA1
7 9 9 P0.6 TBB0
1–8 1, 3, 5–10 1, 3,
5–10
P0.0–
P0.7;
IRTXM,
RX0, TX0,
RX1, TX1,
TBA0/
TBA1,
TBB0/
TBB1
8 10 10 P0.7 TBB1
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.These port pins function as bidirectional I/O pins or as interrupts. All port pins
default to high-impedance mode after a reset. Software must configure these
pins after release from reset to remove the high-impedance input condition. All
interrupt functions must be enabled from software.
32 TQFN40 TQFN44 TQFNPORTSPECIAL FUNCTION 9 11 11 P1.0 INT0
10 12 12 P1.1 INT1
11 13 13 P1.2 INT2
12 14 14 P1.3 INT3
16 19 21 P1.4 INT4
17 20 22 P1.5 INT5
20 23 25 P1.6 INT6
9–12, 16,
17, 20, 21
11–14,
19, 20,
23, 24
11–14,
21, 22,
25, 26
P1.0–
P1.7;
INT0–
INT7
21 24 26 P1.7 INT7
MAXQ610
16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN
32 TQFN40 TQFN44 TQFNNAMEFUNCTION
General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional I/O pins. P2.0–P2.3 default to high-impedance mode after a reset.
Software must configure these pins after release from reset to remove the high-
impedance input condition. All alternate functions must be enabled from
software. Enabling the pin’s special function disables the general-purpose I/O
on the pin.
The JTAG pins (P2.4–P2.7) default to their JTAG function with weak pullups
enabled after a reset. The JTAG function can be disabled using the TAP bit in
the SC register.
P2.7 functions as the JTAG test-data output on reset and defaults to an input
with a weak pullup. The output function of the test data is only enabled during
the TAP’s Shift_IR or Shift_DR states.
32 TQFN40 TQFN44 TQFNPORTSPECIAL FUNCTION — 25 27 P2.0 MOSI
— 26 29 P2.1 MISO
— 29 32 P2.2 SCLK
— 30 33 P2.3 SSEL
24 31 34 P2.4 TCK
25 32 35 P2.5 TDI
26 35 38 P2.6 TMS
24–27
25, 26,
29–32,
35, 36
27, 29,
32–35,
38, 39
P2.0–
P2.7;
MOSI,
MISO,
SCLK,
SSEL,
TCK, TDI,
TMS,
TDO
27 36 39 P2.7 TDO
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.These port pins function as bidirectional I/O pins or as interrupts. All port pins
default to high-impedance mode after a reset. Software must configure these
pins after release from reset to remove the high-impedance input condition. All
interrupt functions must be enabled from software.
32 TQFN40 TQFN44 TQFNPORTSPECIAL FUNCTION — 2 2 P3.0 INT8
— 4 4 P3.1 INT9
— 15 15 P3.2 INT10
— 16 16 P3.3 INT11
— 27 30 P3.4 INT12
— 28 31 P3.5 INT13
— 33 36 P3.6 INT14
2, 4, 15,
16, 27,
28, 33, 34
2, 4, 15,
16, 30,
31, 36,
P3.0–
P3.7;
INT8–
INT15
— 34 37 P3.7 INT15
NO CONNECTION PINS 23 — — N.C.
No Connection. Reserved for future use. Leave this pin unconnected.
MAXQ610
Detailed Description
The MAXQ610 microcontroller provides integrated, low-
cost solutions that simplify the design of IR communica-
tions equipment such as universal remote controls.
Standard features include the highly optimized, single-
cycle, MAXQ 16-bit RISC core, 64KB of flash memory,
2KB data RAM, a soft stack, 16 general-purpose regis-
ters, and three data pointers. The MAXQ core offers the
industry’s best MIPS/mA rating, allowing developers to
achieve the same performance as competing micro-
controllers at substantially lower clock rates. Combining
lower active-mode current with the MAXQ610 stop-
mode current (0.2µA typical) results in increased bat-
tery life. Application-specific peripherals include
flexible timers for generating IR carrier frequencies and
modulation, a high-current IR drive pin capable of sink-
ing up to 25mA current, and output pins capable of
sinking up to 5mA ideal for IR applications, general-
purpose I/O pins ideal for keypad matrix input, and a
power-fail-detection circuit to notify the application
when the supply voltage is nearing the minimum oper-
ating voltage of the microcontroller.
At the heart of the MAXQ610 is the MAXQ 16-bit RISC
core. The MAXQ610 operates from DC to 12MHz and
almost all instructions execute in a single clock cycle
(83.3ns at 12MHz), enabling nearly 12MIPS true code
operation. When active device operation is not
required, an ultra-low-power stop mode can be invoked
from software resulting in quiescent current consump-
tion of less than 0.2µA typical and 2.0µA maximum. The
combination of high-performance instructions and ultra-
low stop-mode current increases battery life over com-
peting microcontrollers. An integrated POR circuit with
brownout support resets the device to a known condi-
tion following a power-up cycle or brownout condition.
Additionally, a power-fail warning flag is set and a
power-fail interrupt can be generated when the system
voltage falls below the power-fail warning voltage,
VPFW. The power-fail warning feature allows the appli-
cation to notify the user that the system supply is low
and appropriate action should be taken.
Microprocessor
The MAXQ610 is based on Maxim’s MAXQ core. The
MAXQis a low-power implementation of the new 16-bit
MAXQfamily of RISC cores. The core supports the
Harvard memory architecture with separate 16-bit pro-
gram and data address buses. A fixed 16-bit instruction
word is standard, but data can be arranged in 8 or 16
bits. The MAXQ core in the MAXQ610 family is imple-
mented as a pipelined processor with performance
approaching 1MIPS per MHz. The 16-bit data path is
implemented around register modules, and each regis-
ter module contributes specific functions to the core.
The accumulator module consists of sixteen 16-bit regis-
ters and is tightly coupled with the arithmetic logic unit
(ALU). A configurable soft stack supports program flow.
Execution of instructions is triggered by data transfer
between functional register modules or between a func-
tional register module and memory. Because data
movement involves only source and destination mod-
ules, circuit-switching activities are limited to active
modules only. For power-conscious applications, this
approach localizes power dissipation and minimizes
switching noise. The modular architecture also provides
a maximum of flexibility and reusability that is important
for a microprocessor used in embedded applications.
The MAXQ instruction set is highly orthogonal. All arith-
metical and logical operations can use any register in
conjunction with the accumulator. Data movement is
supported from any register to any other register.
Memory is accessed through specific data-pointer reg-
isters with automatic increment/decrement support.
Memory
The MAXQ610 incorporates several memory types that
include the following:64KB program flash2KB SRAM data memory5.25KB utility ROMSoft stack
Block Diagram
16-BIT MAXQ
RISC CPU
8kHz NANO
RING
2KB SRAM
IR TIMER
SPI
USART0
USART1
64KB FLASH
SECURE MMU
16-BIT TIMER16-BIT TIMER
GPIO
VOLTAGE
MONITOR
IR DRIVERREGULATOR
WATCHDOG
CLOCK
4KB ROM
MAXQ610
16-Bit Microcontroller with Infrared Module
MAXQ610
16-Bit Microcontroller with Infrared Module
Memory Protection
The optional memory-protection feature separates code
memory into three areas: system, user loader, and user
application. Code in the system area can be kept confi-
dential. Code in the user areas can be prevented from
reading and writing system code. The user loader can
also be protected from user application code.
Memory protection is implemented using privilege lev-
els for code. Each area has an associated privilege
level. RAM/ROM are assigned privilege levels as well.
Refer to the MAXQ610 User’s Guide for a more thor-
ough explanation of the topic. See Table1.
Stack Memory
A 16-bit-wide internal stack provides storage for program
return addresses and can also be used general-purpose
data storage. The stack is used automatically by the
processor when the CALL, RET, and RETI instructions
are executed and when an interrupt is serviced. An
application can also store values in the stack explicitly by
using the PUSH, POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vector-
ing operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value at SP and then
decrement SP.
Utility ROM
The utility ROM is a 5.25KB block of internal ROM mem-
ory that defaults to a starting address of 8000h. The util-
ity ROM consists of subroutines that can be called from
application software. These include the following:In-system programming (bootstrap loader) using
JTAG interfaceIn-circuit debug routinesTest routines (internal memory tests, memory loader,
etc.)User-callable routines for in-application flash pro-
gramming and fast table lookup
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special rou-
tines mentioned. Routines within the utility ROM are
user accessible and can be called as subroutines by
the application software. More information on the utility
ROM functions is contained in the MAXQ610 User’s
Guide.
Some applications require protection against unautho-
rized viewing of program code memory. For these
applications, access to in-system programming, in-
application programming, or in-circuit debugging func-
tions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
Three password locks are provided for protection of up
to three different program memory segments. When the
PWL is set to 1 (POR default) and the contents of the
memory at addresses 0010h to 001Fh are any value
other than FFh or 00h, the password is required to
access the utility ROM, including in-circuit debug and
in-system programming routines that allow reading or
writing of internal memory. When PWL is cleared to 0,
these utilities are fully accessible without password.
The password is automatically set to all ones following
a mass erase.
Watchdog Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execu-
tion is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the appli-
cation software. If software is operating correctly, the
counter is periodically reset and never reaches its max-
imum count. However, if software operation is interrupt-
ed, the timer does not reset, triggering a system reset
and optionally a watchdog timer interrupt. This protects
the system against electrical noise or ESD upsets that
could cause uncontrolled processor operation. The
internal watchdog timer is an upgrade to older designs
with external watchdog devices, reducing system cost
and simultaneously increasing reliability.
AREAPAGE ADDRESSMAXIMUM PRIVILEGE LEVEL
System 0 to ULDR-1 High
User Loader ULDR to UAPP-1 Medium
User Application UAPP to top Low
Utility ROM N/A High
Other (RAM) N/A Low
Table 1. Memory Areas and Associated Maximum Privilege Levels
MAXQ610
16-Bit Microcontroller with Infrared Module
The watchdog timer functions as the source of both the
watchdog-timer timeout and the watchdog-timer reset.
The timeout period can be programmed in a range of
215to 224system clock cycles. An interrupt is generat-
ed when the timeout period expires if the interrupt is
enabled. All watchdog-timer resets follow the pro-
grammed interrupt timeouts by 512 system clock
cycles. If the watchdog timer is not restarted for another
full interval in this time period, a system reset occurs
when the reset timeout expires. See Table2.
IR Carrier Generation and
Modulation Timer
The dedicated IR timer/counter module simplifies low-
speed IR communication. The IR timer implements two
pins (IRTX and IRRX) for supporting IR transmit and
receive, respectively. The IRTX pin has no correspond-
ing port pin designation, so the standard PD, PO, and
PI port control status bits are not present. However, the
IRTX pin output can be manipulated high or low using
the PWCN.IRTXOUT and PWCN.IRTXOE bits when the
IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of two separate timing enti-
ties: a carrier generator and a carrier modulator. The
carrier generation module uses the 16-bit IR Carrier
register (IRCA) to define the high and low time of the
carrier through the IR carrier high byte (IRCAH) and IR
carrier low byte (IRCAL). The carrier modulator uses the
IR data bit (IRDATA) and IR Modulator Time register
(IRMT) to determine whether the carrier or the idle con-
dition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the begin-
ning value for the carrier modulator. During transmis-
sion, the IRV register is initially loaded with the IRMT
value and begins down counting towards 0000h,
whereas in receive mode it counts upward from the ini-
tial IRV register value. During the receive operation, the
IRV register can be configured to reload with 0000h
when capture occurs on detection of selected edges or
can be allowed to continue free-running throughout the
receive operation. An overflow occurs when the IR timer
value rolls over from 0FFFFh to 0000h. The IR overflow
flag (IROV) is set to 1 and an interrupt is generated if
enabled (IRIE = 1).
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0]
Carrier Frequency (fCARRIER) =
fIRCLK/(IRCAH + IRCAL + 2)
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for
each IRV downcount interval and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV downcount interval so that duty-cycle variation
and frequency shifting is possible from one interval to
the next, which is illustrated in Figure 1.
Figure 2 illustrates the basic carrier generation and its
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
IR Transmission
During IR transmission (IRMODE = 1), the carrier gener-
ator creates the appropriate carrier waveform, while the
carrier modulator performs the modulation. The carrier
modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV downcounter is
clocked by the carrier frequency and thus the modula-
tion is a function of carrier cycles. When IRCFME = 1,
the IRV downcounter is clocked by IRCLK, allowing car-
rier modulation timing with IRCLK resolution.
WD[1:0]WATCHDOG CLOCKWATCHDOG INTERRUPT TIMEOUTWATCHDOG RESET AFTER
WATCHDOG INTERRUPT (μs)
00 Sysclk/215 2.7ms 42.7
01 Sysclk/218 21.9ms 42.7
10 Sysclk/221 174.7ms 42.7
11 Sysclk/224 1.4s 42.7
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
MAXQ610
16-Bit Microcontroller with Infrared ModuleSAMPLE
IRDATA ON
IRV = 0000h
CARRIER MODULATION
CARRIER GENERATION
CARRIERIRCLK
IRCFMEIRCAL + 1IRCAH + 1
IRDATA
IRMT
IRTXPOL
IRTX PIN
IR INTERRUPT
CARRIER OUTPUT
(IRV)
IRDATA
IR INTERRUPT1
IRMT = 3
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
IRCA
IRMTIRMT = 5
IRCA = 0202hIRCA = 0002h
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWNCOUNT INTERVAL 20543210
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
MAXQ610
16-Bit Microcontroller with Infrared Module
The IRTXPOL bit defines the starting/idle state as well
as the carrier polarity for the IRTX pin. If IRTXPOL = 1,
the IRTX pin is set to a logic-high when the IR timer
module is enabled. If IRTXPOL = 0, the IRTX pin is set
to a logic-low when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to
determine whether the carrier generator output is out-
put to the IRTX pin for the next IRMT carrier cycles.
When IRDATA = 1, the carrier waveform (or inversion of
this waveform if IRTXPOL = 1) is output on the IRTX pin
during the next IRMT cycles. When IRDATA = 0, the
idle condition, as defined by IRTXPOL, is output on the
IRTX pin during the next IRMT cycles.
The IR timer acts as a downcounter in transmit mode.
An IR transmission starts when 1) the IREN bit is set to
1 when IRMODE = 1, 2) the IRMODE bit is set to 1
when IREN = 1, or 3) when IREN and IRMODE are both
set to 1 in the same instruction. The IRMT and IRCA
registers, along with the IRDATA and IRTXPOL bits, are
sampled at the beginning of the transmit process and
every time the IR timer value reloads its value. When
the IRV reaches 0000h value, on the next carrier clock,
it does the following:Reloads IRV with IRMT.Samples IRCA, IRDATA, and IRTXPOL.Generates IRTX accordingly.Sets IRIF to 1.Generates an interrupt to the CPU if enabled (IRIE = 1).
To terminate the current transmission, the user can
switch to receive mode (IRMODE = 0) or clear IREN to 0.
Carrier Modulation Time = IRMT + 1 carrier cycles
IR Transmit—Independent External Carrier
and Modulator Outputs
The normal transmit mode modulates the carrier based
upon the IRDATA bit. However, the user has the option
to input the modulator (envelope) on an external pin if
desired. If the IRENV[1:0] bits are configured to 01b or
10b, the modulator/envelope is output to the IRTXM pin.
The IRDATA bit is output directly to the IRTXM pin (if
IRTXPOL = 0) on each IRV downcount interval bound-
ary just as if it were being used to internally modulate
the carrier frequency. If IRTXPOL = 1, the inverse of the
IRDATA bit is output to the IRTXM pin on the IRV inter-
val downcount boundaries. The envelope output is illus-
trated in Figure 4. When the envelope mode is enabled,
it is possible to output either the modulated (IRENV[1:0]
= 01b) or unmodulated (IRENV[1:0] = 10b) carrier to
the IRTX pin.
CARRIER OUTPUT
(IRV)
IRDATA
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 010
IRMT = 33102310
Figure 3. IR Transmission Waveform (IRCFME = 0)
