MAXQ1103 Fast Delivery |IC PHOENIX CO.,LIMITED

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MAXQ1103
DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography
MAXQ1103
EVALUATION KIT AVAILABLE
DeepCover Secure Microcontroller with Rapid
Zeroization Technology and Cryptography
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
General Description
DeepCover™ embedded security solutions cloak sensi-tive data under multiple layers of advanced physicalsecurity to provide the most secure key storage possible.
The DeepCover Secure Microcontroller (MAXQ1103) isa low-power, 32-bit RISC device that combines high-performance, single-cycle processing, sophisticatedtamper-detection technology, and cryptographic hard-ware. Advanced security features are designed to meetthe stringent requirements of regulations such as ITSECE3 High, FIPS 140-2 Level 3, and the Common CriteriaCertifications. The MAXQ1103 is targeted at electroniccommerce, banking, and data security systems thatrequire the highest levels of secure access control,secure data storage, digital signature, or certificateauthentication. A secure memory protection unit pro-tects critical internal and external memory against tam-pering with triple-DES (3DES) encryption. Activation of atamper sensor causes a rapid zeroization of criticaldata. An internal physical shield layer increases thecomplexity and cost of a physical attack against the die.
A 32-bit MAXQ30 core powers the cryptographicallysecure MAXQ1103. Applications are supported with512KB of high-performance internal flash memory forcode/data storage and 32KB SRAM. Up to 8MB ofadditional external program and data memory is sup-ported through a dedicated word-wide memory buswith programmable wait states. Additional peripheralssuch as serial I/O, 16-bit timers, hardware math accel-erator, ISO 7816 UART, and a USB controller increasesystem utility while reducing component count.
System security is enhanced by the addition of high-speed cryptographic hardware accelerators forECDSA, DSA, RSA, Secure Hash Algorithm, and triple-key 3DES. The embedded hash engine supports multi-ple hash functions recommended by the NationalInstitute of Standards and Technology (NIST). The truehardware random-number generator (RNG) supportsFIPS 186-2 with an available software library.
Applications
FeaturesHigh-Performance 32-Bit MAXQ30 RISC CoreDC to 25MHz Operation, Approaching 1MIPS per MHzDual 1.8V Core/3.3V I/O Enables Low Power/
Flexible Interfacing5V Tolerant I/OUp to 32 General-Purpose I/O Pins34 Instructions, Most Single CycleThree Independent Data Pointers Accelerate Data
Movement with Automatic Increment/DecrementVirtually Unlimited Software Stack16-Bit Instruction Word, 32-Bit Internal Data Bus16 x 32-Bit AccumulatorsSecurity Features
3DES-Encrypted External Memory Bus
Prevents Eavesdropping
Tamper Sensors Rapidly “Zeroize” Internal Keys
and User Data When:
Out-of-Range Temperature/Voltage Detected
User-Defined Self-Destruct Inputs (SDIx) Activated
Internal Cryptographic Hardware Includes:
DES Engine Supporting Single DES and 2/3-Key
3DES Operations
Public-Key Cryptographic Accelerator for
ECDSA (160-, 192-, and 256-Key Strength)
Public-Key Cryptographic Accelerator for
DSA and RSA (1024- and 2048-Key Strength)
Hardware Hash Engine Supports SHA-1,
SHA-224, and SHA-256
Unresettable True-Time Clock Self-Imposes
Expiration Dates and Date/TimestampingMemory Features
Secure Memory Protection Unit and 4KB
Instruction Cache
512KB of Internal Flash Program Memory
3KB Internal Program Memory SRAM
32KB Internal Data SRAM, Including 1KB Battery-
Backed NV SRAM
Linear Address Space Directly Accesses Up to
8MB of External Program/Data MemoryPeripheral Features
USB Device Controller with Four Endpoint Buffers
ISO 7816 UART with FIFO with Two Physically
Separate Communication BusesPower Management FeaturesIn-System Programming Through Debug Port orSerial PortUltra-Low Battery Leakage to Support NV RAMand Security Sensors (150nA)
Ordering Information
DeepCover is a trademark and MAXQ is a registered trademark of
Maxim Integrated Products, Inc.
EMV is a registered trademark of EMVCo, LLC.See the Detailed Featuressection for complete list of features.
PART TEMP
RANGE
PIN-
PACKAGE
TAMPER
RESPONSIVE
MAXQ1103-ENS+ -40°C to +85°C 144 TQFP Yes
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
Electronic Commerce
PCI Terminals
PIN Pads
ATM Keyboards
EMV®Banking
Secure Access Control
Secure Data Storage
Pay-per-Play
Certificate Authentication
Electronic Signature Generator
ABRIDGED DATASHEET
DeepCover Secure Microcontroller with Rapid
Zeroization Technology and Cryptography
MAXQ1103
Note to readers:This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maximintegrated.com/MAXQ1103and click on Request Full Data Sheet.
Functional Diagram
2048-BIT MODULO
ARITHMETIC
ACCELERATOR
MAXQ30
PIPELINED
RISC CORE
INTERNAL DATA MEMORY
INTERNAL PROGRAM
MEMORY
MMU
DATA MEMORY
ENCRYPTOR/
DECRYPTOR
16K x 16
SRAM
HIGH/LOW
TEMPERATURE SENSORS
EXTERNAL CODE
INTEGRITY CHECKER
DES/3DES
PROGRAM MEMORY
DECRYPTOR
INSTRUCTION
CACHE
2K x 16
512 x 16
SRAM
16K x 16
ROM
256K x 16
FLASH
1.5K x 16
SRAM
DES KEYS
EXTERNAL PROGRAM AND DATA MEMORY INTERFACE
RANDOM-NUMBER
GENERATOR (RNG)
CRC-16/32
GENERATOR
REAL-TIME
CLOCK
CLOCK
GENERATION
INTERNAL
20MHz OSC
WATCHDOG
PLL (4X/2X)
BATTERY BACKED
32KIN
32KOUT
GND2
RESET AND
DESTRUCT
RESET
RESET
PROG
SDI[1:7]
HFXIN
HFXOUT
SDBE
POWER-
SUPPLY
MONITORING
DES/3DES
USER ENGINE
INTERNAL
55MHz OSC
MULTIPLY-
ACCUMULATE UNITSHAB1B2B3
PCS1
PCS1N
PCS2
PCS2N
DCS1
DCS1N
DCS2
DCS2N
PES1PES2
ED[31:0]
AD[19:0]
USB
VDDIO (+3.3V)
VDD (+1.8V)
VBAT (+3V)
GND
VRST
VDDO
R/W
USART 0
TIMER 2
JTAG
PORT 3
TIMER 3
PORT 2
EDGE INTERRUPTS
TIMER 1
USART 1
PORT 1
TIMER 0
ISO 7816
UART AND
FIFO
PORT 0
MAXQ1103
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.

Partno	Mfg	Dc	Qty	Available	Descript
MAXQ1103	MAXIM	N/a	7	avai	DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography