MAX9667ETP+ ,6/8/10-Channel, 10-Bit, Nonvolatile Programmable Gamma and VCOM Reference VoltagesELECTRICAL CHARACTERISTICS(V = V = 15.7V, V = 3.3V, V = 0V, VCOM connected to FB, CTL = DVDD/2, no ..
MAX9667ETP+T ,6/8/10-Channel, 10-Bit, Nonvolatile Programmable Gamma and VCOM Reference VoltagesApplicationsTFT LCDs10 OUT0DACOrdering InformationGAMMA PIN- OUT110DACPART TEMP RANGECHANNELS PACKA ..
MAX9669ETI+ ,10-Bit Programmable Gamma Reference System with MTP for TFT LCDsApplications 10 1010-BITGMA1DAC10 1010-BITTFT LCDsGMA2DAC10 10 10-BITGMA3DACPin Configuration10 101 ..
MAX9669ETI+T ,10-Bit Programmable Gamma Reference System with MTP for TFT LCDsELECTRICAL CHARACTERISTICS(V = 18V, V = 18V, V = 3.3V, V = V = V = 0, VCOM = VCOM_FB, no load, T = ..
MAX966ESA ,Single/Dual/Quad / Micropower / Ultra-Low-Voltage / Rail-to-Rail I/O ComparatorsGeneral Description ________
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MB89163 ,8-bit Proprietary MicrocontrollerFUJITSU SEMICONDUCTORDS07-12405-2EDATA SHEET8-bit Proprietary MicrocontrollerCMOS2F MC-8L MB89160/1 ..
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MAX9667ETP+-MAX9667ETP+T
6/8/10-Channel, 10-Bit, Nonvolatile Programmable Gamma and VCOM Reference Voltages
General DescriptionThe MAX9665/MAX9666/MAX9667 provide multiple
programmable reference voltages for gamma correc-
tion in TFT LCDs and a programmable reference volt-
age for VCOM adjustment. All gamma and VCOM
reference voltages have a 10-bit digital-to-analog con-
verter (DAC) and buffer with high peak current. This
reduces the recovery time of the output voltage when
critical levels and patterns are displayed.
These devices include multiple-time programmable
(MTP) memory to store gamma and VCOM codes on
the chip, eliminating the need for external EEPROM.
The MTP memory supports up to 300 write operations.
The MAX9665/MAX9666/MAX9667 feature an I2C inter-
face to control the programmable reference voltages
and a single-wire interface to toggle the VCOM refer-
ence voltage up or down.
ApplicationsTFT LCDs
Features6/8/10 Channels Gamma Correction, 10-Bit
ResolutionVCOM DriverIntegrated Multiple-Time Programmable MemoryDAC Reference InputSingle-Wire and I2C Programming of VCOM
Reference950mA Peak Transient Current on VCOM Channel
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages19-5000; Rev 4; 7/10
DAC
DAC
DAC
DAC
DAC
DAC
DAC
VCOM
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
I2C
REGISTERSMTP
MEMORY
I2C
SINGLE-WIRE
INTERFACE
DVDD
AVDD
REF
SCL
SDA
CTL
GND
MAX9665
Functional Diagrams
Ordering Information
PARTGAMMA
CHANNELSTEMP RANGEPIN-
PACKAGE
MAX9665ETP+6- 40°C to + 85° C 20 TQFN-EP*
MAX9666ETP+8- 40°C to + 85° C 20 TQFN-EP*
MAX9667ETP+10- 40°C to + 85° C 20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAX9665
THIN QFN5mm x 5mmTOP VIEW
EP*
+DVDD
SDA
GND
N.C.N.C.OUT2OUT0
VCOM
CTL
N.C.
OUT4
N.C.
OUT5
*EP = EXPOSED PAD. CONNECT TO DIGITAL GROUND PLANE.
SCL
OUT1
AVDD
OUT3REF4514121110
Pin ConfigurationsPin Configurations continued at end of data sheet.
Functional Diagrams continued at end of data sheet.
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages
AVDD to GND.....................................................-0.3V to +22V
DVDD to GND.......................................................-0.3V to +4V
Outputs
OUT0–OUT9, VCOM to GND.............-0.3V to (VAVDD+ 0.3V)
Inputs
SDA, SCL, CE to GND..........................................-0.3V to +4V
CTL, REF to GND...............................................-0.3V to +22V
FB to GND..........................................-0.3V to (VAVDD+ 0.3V)
Continuous Current
OUT0–OUT9, VCOM...................................................±400mA
All Other Pins................................................................±50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TQFN (derate 25.6mW/°C above +70°C)....2051.3mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
20-Pin TQFN...................................................................6°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
20-Pin TQFN.................................................................39°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLIESAnalog-Supply Voltage RangeVAVDDGuaranteed by power-supply rejection
ratio specification (Note 3)920V
Analog-Supply Voltage Range for
Programming MTPVAVDD_MTP1520V
Digital-Supply Voltage RangeVDVDD2.73.6V
MAX96651222
MAX96661424Analog Quiescent CurrentIAVDD
MAX96671626
Digital Quiescent CurrentIDVDDNo SCL or SDA transitions450900µA
DVDD Undervoltage LockoutUVLO2.32.6V
DACResol uti on10Bits
Integ r al N onl i near i ty E r r or IN LTA = +25°C, 16 ≤ CODE ≤ 10081LSBi ffer enti al N onl i near i ty E r r or D N LTA = +25°C, 16 ≤ CODE ≤ 10081LSB
REF Input Resistance384kΩ
GAMMA OUTPUTS (Note 4)hor t- C i r cui t C ur r entIS C Outp ut to AV D D or GN D , TA = +25°C100400mAaxi m um C ap aci ti ve Load Placed directly at output300pF
Output ImpedanceZOOutput resistance when output is disabled84kΩ
Load Reg ul ati onREG- 5m A to + 5m A0.5mV/mA
Total Outp ut E r r or TA = +25°C, m easur ed at cod e = 512-40+40mVl ew RateS R5V sw i ng , m easur e 10% to 90%22V/µs
Note 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLow Outp ut V ol tag eV M IN S i nki ng 4m A, TA = +25°C0.10.15Vi g h Outp ut V ol tag eV M AX S our ci ng 4m A, TA = +25°CV AV D D
- 0.15AV D D
- 0.1V
To AV D D , f = 60kH z, RE F and AV D D shor ted 40P ow er - S up p l y Rej ecti on Rati oP S RR9V < V AV D D < 20V , V RE F = 9V 6090dB
Channel-to-Channel IsolationCXTLKf = 5MHz, all channels to all channels80dB
GAMMA OUTPUTS (Note 5)Short-Circuit CurrentISCOutputs to AVDD or GND, TA = +25°C50200mAaxi m um C ap aci ti ve Load Placed directly at output300pF
Output ImpedanceZOOutput resistance when output is disabled84kΩ
Load RegulationREG-5mA to +5mA0.50mV/mA
Total Output ErrorTA = +25°C, m easur ed at cod e = 512-40+40mV
Slew RateSRSwing 5VP-P at input, 10% to 90%
measurement on output22V/µs
Low Outp ut V ol tag eV M IN S i nki ng 4m A0.150.2Vi g h Outp ut V ol tag eV M AX S our ci ng 4m AV AV D D -
0.2AV D D
- 0.15V
To AV D D , f = 60kH z, RE F and AV D D shor ted 40P ow er - S up p l y Rej ecti on Rati oP S RR9V < V AV D D < 20V , V RE F = 9V 6090dB
Thermal Shutdown160°C
Thermal-Shutdown Hysteresis15°C
Channel-to-Channel IsolationCXTLKf = 5MHz, all channels to all channels80dB
VCOM OUTPUTShort-Circuit CurrentISCOutputs to AVDD or GND, TA = +25°C50200mAaxi m um C ap aci ti ve Load Placed directly at output300pF
Output ImpedanceZOOutput resistance when output is disabled84kΩ
Load RegulationREG-5mA to +5mA±0.2mV/mA
Total Output ErrorTA = +25°C, measured at code = 512-501+50mV
Slew RateSRS w i ng 4V P - P at V C O M , 10% to 90% ,
RL = 10kΩ, CL = 50pF (Note 6)100V/µs
Low Outp ut V ol tag eV M IN S i nki ng 4m A0.150.2Vi g h Outp ut V ol tag eV M AX S our ci ng 4m AV AV D D
- 0.2AV D D
- 0.15V
To AV D D , f = 60kH z, RE F and AV D D shor ted 40P ow er - S up p l y Rej ecti on Rati oP S RR9V < V AV D D < 20V , V RE F = 9V 70dB
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-WIRE INTERFACEE Inp ut Low V ol tag e2.6V < V D V D D < 3.6V 0.3 xD V D D VE Inp ut H i g h V ol tag e2.6V < V D V D D < 3.6V 0.7 xD V D D VE S tar tup Ti m e( N ote 7) 1msTL H i g h V ol tag e2.6V < V D V D D < 3.6V 0.7 xD V D D
0.82 xD V D D VTL Fl oat V otl ag e2.6V < V D V D D < 3.6V 0.4 xD V D D
0.62 xD V D D V
CTL Low Voltage2.6V < V D V D D < 3.6V 0.2 xD V D D
0.32 xD V D D V
CTL Rejected Pulse Width20µs
CTL Typical Pulse Width50µs
CTL Minimum Pulse Width200µsTL M i ni m um Ti m e Betw een P ul ses10µs
CTL = GND-10CTL Input CurrentCTL = DVDD+10µA
LOGIC INPUTS AND OUTPUTS (SDA, SCL)Input High VoltageVIH0.7 xD V D D V
Input Low VoltageVIL0.3 xD V D D V
Input Leakage CurrentIIH, IILVSDA/SCL = 0V or V D V D D -10+0.01+10µA
Input Capacitance(Note 7)5pF
Power-Down Input CurrentISDA/SCLVDVDD = 0V, VSDA/SCL = 1.98V-10+10µA
SDA Output Low VoltageVOLISINK = 6mA0.4V
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2C TIMING CHARACTERISTICS (Figure 4)Serial-Clock FrequencyfSCL0400kHz
Bus Free Time Between STOP
and START ConditionstBUF1.3µs
Hold Time (Repeated) START
ConditiontHD,STA0.6µs
SCL Pulse-Width LowtLOW1.3µs
SCL Pulse-Width HightHIGH0.6µs
Setup Time for a Repeated
START ConditiontSU,STA0.6µs
Data Hold TimetHD,DAT0900ns
Data Setup TimetSU,DAT100ns
SDA and SCL Receiving Rise
TimetR(Note 8)20 +
0.1CB300ns
SDA and SCL Receiving Fall
TimetF(Note 8)20 +
0.1CB300ns
SDA Transmitting Fall TimetF,TX(Note 8)20 +
0.1CB250ns
Setup Time for STOP ConditiontSU,STO0.6µs
Bus CapacitanceCB400pF
Pulse Width of Suppressed SpiketSP050ns
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
Note 2:All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 3:For AVDD below 15.6V, internal LDO must be externally adjusted to meet LDO dropout specification.
Note 4:This section applies to OUT0, OUT2, OUT3, and OUT5 of the MAX9665; OUT0, OUT3, OUT4, and OUT7 of the MAX9666;
OUT0, OUT4, OUT5, and OUT9 of the MAX9667.
Note 5:This section applies to OUT1 and OUT4 of the MAX9665; OUT1, OUT2, OUT5, and OUT6 of the MAX9666; OUT1, OUT2,
OUT3, OUT6, OUT7, and OUT8 of the MAX9667.
Note 6:Measured with the VCOM amplifier configured as an inverting unity-gain amplifier. RF= RIN= 10kΩ.
Note 7:Guaranteed by design. Not production tested.
Note 8:CBis in pF.
OUTPUT OFFSET
VOLTAGE DISTRIBUTION
MAX9665 toc01
OUTPUT OFFSET (mV)
N (%)2012-44-12-20-28
CODE 512
OUT2
GAMMA LOAD REGULATION
MAX9665 toc02
LOAD CURRENT (mA)
VOLTAGE DEVIATION (mV)10-15-10-505
VCOM LOAD REGULATION
MAX9665 toc03
LOAD CURRENT (mA)
VOLTAGE DEVIATION (mV)10-15-10-505
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc04
DAC CODE
INL (LSB)
VREF = 15.7V
OUT2
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc05
DAC CODE
INL (LSB)
VREF = 15.7V
VCOM
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc06
INL (LSB)
VREF = 10V
OUT2
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc07
INL (LSB)
VREF = 10V
VCOM
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Characteristics(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc08
DAC CODE
INL (LSB)
VREF = 5V
OUT2
INTEGRAL NONLINEARITY
vs. DAC CODE
MAX9665 toc09
DAC CODE
INL (LSB)
VREF = 5V
VCOM
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc10
DAC CODE
DNL (LSB)
VREF = 15.7V
OUT2
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc11
DAC CODE
DNL (LSB)
VREF = 15.7V
VCOM
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc12
DAC CODE
DNL (LSB)
VREF = 10V
OUT2
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc13
DNL (LSB)
VREF = 10V
VCOM
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc14
DNL (LSB)
VREF = 5V
OUT2
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Characteristics (continued)(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Characteristics (continued)(VAVDD= VREF= 15.7V, VDVDD= 3.3V, VGND= 0V, VCOM connected to FB, CTL = DVDD/2, no load, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at TA= +25°C.) (Note 2)
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
MAX9665 toc15
DAC CODE
DNL (LSB)
VREF = 5V
VCOM
POWER-SUPPLY REJECTION RATIO
OF GAMMA OUTPUTS vs. FREQUENCY
MAX9665 toc16
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VAVDD = VREF = 15.7V ± 100mVP-P
POWER-SUPPLY REJECTION RATIO
OF VCOM vs. FREQUENCY
MAX9665 toc17
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VAVDD = VREF = 15.7V ± 100mVP-P
REF POWER-SUPPLY REJECTION RATIO
OF GAMMA OUTPUTS vs. FREQUENCY
MAX9665 toc18
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VREF = 15.7V ± 100mVP-P
REF POWER-SUPPLY REJECTION RATIO
OF VCOM vs. FREQUENCY
MAX9665 toc19
FREQUENCY (Hz)
PSRR (dB)100k
10k10M
VREF = 15.7V ± 100mVP-P
GAMMA LOAD TRANSIENT (±100mA)
MAX9665 toc20
100mA/div
GAMMA LOAD CURRENT
GAMMA OUTPUT0
500mV/div
2µs/div
VCOM LOAD TRANSIENT (±500mA)
MAX9665 toc21
200mA/div
VCOM LOAD CURRENT
VCOM OUTPUT
500mV/div
2µs/div
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Pin Description
PIN
MAX9665MAX9666MAX9667NAMEFUNCTION111CE
Single-Wire Control Interface Enable. Connect CE to DVDD to
enable the CTL input. Connect CE to GND to disable the CTL
input and reduce the supply current.22DVDDDigital Supply Input. Bypass to GND with 0.1µF capacitor.
333SCLI2C Serial-Clock Input
444SDAI2C Serial-Data Input/Output55GNDGround—6OUT9Gamma Output 9—7OUT8Gamma Output 868OUT7Gamma Output 779OUT6Gamma Output 6810OUT5Gamma Output 51011OUT4Gamma Output 41112OUT3Gamma Output 31313OUT2Gamma Output 21414OUT1Gamma Output 11515OUT0Gamma Output 01616REFReference Input1717AVDDAnalog Supply Input. Bypass AVDD to GND with a minimum
0.1µF capacitor.1818FBVCOM Amplifier Negative Input1919VCOMVCOM Amplifier Output2020CTL
VCOM Adjustment and Multiple-Time Programmable Memory
Control. CTL sets the internal DAC code and programs the
MTP memory. A pulse-control method is used to adjust the
VCOM level. See the VCOM Adjustment (CTL) section. To
program the DAC setting into the MTP memory as the power-
on default, drive CTL to the MTP programming voltage using
the correct timing and voltage ramp rates. See the MTP
Programming (CTL) section.
7, 9, 12, 149, 12—N.C.No Connection. Not internally connected.——EPExposed Pad. The exposed pad must be connected to GND.
MAX9665/MAX9666/MAX9667
Detailed DescriptionThe MAX9665/MAX9666/MAX9667 are a family of multi-
channel, programmable reference voltages. Each
channel has a 10-bit DAC to create the reference volt-
age. One channel has an operational amplifier that fol-
lows the DAC while all other channels have a buffer
after the DAC. The user can program the DAC codes
into on-chip nonvolatile memory, which is called multi-
ple-time programmable (MTP) memory since data can
be written into it up to 300 times.
The MAX9665/MAX9666/MAX9667 provide the gamma,
VCOM, and level shifter reference voltages in a LCD
panel. A single chip can potentially replace a discrete
digital variable resistor (DVR), VCOM amplifier, gamma
buffers, high-voltage linear regulator, and resistor
strings. The high-voltage linear regulator can be elimi-
nated because the DAC contains a lowpass filter that
reduces horizontal line frequency noise by 40dB. Power
sequencing is well-controlled since a single chip gener-
ates all the various reference voltages needed for the
LCD panel.
Each part has an I2C interface for programming both
the MTP memory and the I2C registers. For compatibili-
ty with legacy flicker adjustment production equipment,
these devices include a single-wire interface that is
compatible with the MAX1512.
With the MTP memory and the I2C interface, these
devices enable automatic gamma and flicker calibra-
tion on a panel-by-panel basis on the production line.
Contact your Maxim representative for more details.
10-Bit Digital-to-Analog ConvertersThe reference input, REF, accepts a DC voltage
between ground (GND) and the analog supply voltage
(AVDD). The voltage at REF sets the full-scale output of
the DACs. Determine the output voltage using the fol-
lowing equations:
VOUT = (VREFx CODE)/2N
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX9665 family, N = 10 and CODE ranges from 0 to
Note that even if REF is less than AVDD, the DAC can
never output REF because the maximum value of
CODE is always one LSB less than the reference. For
example, if REF = 16V and CODE = 1023, then the out-
put voltage is:
VOUT = (16V x 1023)/210
= 15.98438V
Gamma BuffersThere are two types of DAC output buffers: 5mA and
10mA. The 5mA buffer is guaranteed to source or sink
5mA of DC current within 0.2V of the supplies, and the
10mA buffer does the same with 10mA. The 10mA
buffers should be attached to the ends of the resistor
ladders that set the transfer function of the source dri-
ver (look at the connections from OUT0, OUT4, OUT5,
and OUT9 on the typical operating circuit of the
MAX9667). The 5mA buffers should be attached to the
middle tap points of the resistor ladder because those
places require less current than the ends (see the con-
nections from OUT1, OUT2, OUT7, and OUT8 on the
typical operating circuit of the MAX9667).
If the 10mA buffers cannot provide enough current to
drive the ends of the resistor ladders, attach an addi-
tional resistor from the nearest supply. For example, at
the very top of the resistor ladder, attach an additional
resistor to AVDD. At the very bottom of the resistor lad-
der, attach an additional resistor to GND. The
MAX9665/MAX9666/MAX9667 greatly diminish any
noise from the AVDD supply through the discrete resis-
tor because the high-frequency noise from REF has
been attenuated, and the buffers have excellent AC
PSRR. See Figure 1.
The source drivers can kick back a great deal of cur-
rent to the buffer outputs during a horizontal line
change or a polarity switch. The 5mA DAC output
buffers can source/sink 200mA of peak transient cur-
rent, and the 10mA DAC output buffers can source/sink
400mA of peak transient current to reduce the recovery
time of the output voltages when critical levels and pat-
terns are displayed.
VCOM AmplifierThe operational amplifier attached to the bottom DAC
holds the VCOM voltage stable while providing the abil-
ity to source and sink 400mA into the backplane of a
TFT-LCD panel. The operational amplifier can directly
drive the capacitive load of the TFT-LCD backplane
without the need for a series resistor in most cases. The
VCOM amplifier has current limiting on its output to pro-
tect its bond wires.
The output (VCOM) and negative input (FB) of the oper-
ational amplifier are typically connected together in a
unity-gain configuration. If higher output current is
required, add an npn emitter follower and a pnp emitter
follower in the feedback loop.
If a higher, closed-loop gain is desired, add feedback
resistors as shown in Figure 2.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference VoltagesDAC
DAC
DAC
DAC
DAC
DACOUT7
OUT6
OUT5
OUT4
OUT3
OUT2
I2C
REGISTERS
MTP
MEMORY
I2C
SINGLE-WIRE
INTERFACE
DVDD
SCL
SDA
CTL
GND
DAC10OUT8
DAC10OUT9
DAC10+
VCOM
AVDD
REF
DAC10OUT1
DAC10OUT0
LCD PANELSOURCE
DRIVER
LEVEL
SHIFTER
AVDD
MAX9667
Figure 1. Pullup and Pulldown Resistors Attached to Source Driver
MAX9665/MAX9666/MAX9667
Multiple-Time Programmable (MTP)
MemoryMTP memory, which is a form of nonvolatile memory,
stores the DAC code values even when the chip is not
powered. When the chip is powered up, the code val-
ues are automatically transferred from MTP memory to
the I2C registers. See the Power-On Reset (POR)/
Power-Upsection for more details.
The user can program DAC codes into MTP memory for
up to 300 times. In conventional TFT-LCD applications, a
resistor string creates the gamma voltages. MTP memory
eliminates the resistor string and the need to change
manually the resistor values when searching for the opti-
mal gamma curve for a new TFT-LCD panel model.
Power-On Reset (POR)/Power-UpThe POR circuit that monitors DVDD ensures that all I2C
registers are reset to their MTP values upon power-up
or POR. Once DVDD rises above 2.4V (typ), the POR
circuit releases the I2C registers and the values stored
in MTP are loaded. Should DVDD drop to less than 2.4V
typical, then the contents of the registers can no longer
be guaranteed and a reset is generated. When DVDD
rises back above the POR voltage, the values stored in
MTP are loaded back into the I2C registers.
The transfer time of the MTP registers to I2C registers is
300µs typical and is less than 400µs in the worst case.
During this time, AVDD should not be powered up, and
the I2C does not acknowledge any commands (the I2C
only starts acknowledging commands after all registers
have been loaded from MTP).
Thermal ProtectionWhen the die temperature reaches +165°C, all gamma
buffers except for the middle ones are disabled. See
Table 1.
When the die cools down by 15°C, all the buffers are
enabled again.
The VCOM operational amplifier does not have thermal
protection.
Digital InterfacesThe MAX9665/MAX9666/MAX9667 have two digital
interfaces: I2C and single-wire. Through the I2C inter-
face, the user can change all the registers and program
MTP memory. The I2C interface is the more general pur-
pose of the two interfaces.
The single-wire interface, which is compatible with the
MAX1512 digital interface, is included to support TFT-
LCD production lines that depend upon the single-wire
interface to adjust the VCOM voltage to minimize flick-
er. Note that the single-wire interface cannot program
the gamma registers or gamma MTP memory.
Interoperability Between the Single-Wire
Interface and the I2C InterfaceTo prevent any collision between the single-wire inter-
face and the I2C interface, operation through one inter-
face is only allowed if the other is in the idle state. For
example, if the I2C interface is in the middle of execut-
ing a command, any input through the single-wire inter-
face is ignored. Conversely, if the single-wire interface
is in the middle of executing a command, the I2C inter-
face does not acknowledge any commands.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference VoltagesMAX9665
MAX9666
MAX9667
VCOM
Figure 2. VCOM Operational Amplifier with Feedback Resistors
PARTENABLEDDISABLEDMAX9665OUT2 and OUT3OUT0, OUT1, OUT4, OUT5
MAX9666OUT3 and OUT4OUT0, OUT1, OUT2, OUT5, OUT6, OUT7
MAX9667OUT4 and OUT5OUT0, OUT1, OUT2, OUT3, OUT6, OUT7, OUT8, OUT9
Table 1. Buffer Output Status During Thermal Shutdown
Bus ArchitectureThe internal memory, both volatile and nonvolatile, is
divided into blocks that are connected by a 10-bit bus
(Figure 3).
The I2C registers (volatile memory) are 8 bits wide. Two
I2C registers are needed to hold one 10-bit DAC code.
The I2C registers are separated into blocks that are dis-
tinguished by whether they hold VCOM DAC codes or
gamma DAC codes. MTP memory (nonvolatile memory)
is organized in the same manner. The VCOM MTP
memory has enough bits to store the single VCOM DAC
code. Likewise, the gamma MTP memory has enough
bits to store all of the gamma DAC codes. Each block
connected to the 10-bit bus has a unique location num-
ber with one exception. The block that contains the bus
master, I2C interface, and the single-wire interface does
not store any data, and hence, it does not have a loca-
tion number.
Although the external I2C interface transfers data in
units of 8 bits (1 byte), the internal bus that connects
the I2C registers, MTP memory, and digital interfaces is
10 bits wide because the DAC code size is 10 bits. The
10-bit bus can also accommodate data transfers of
fewer than 10 bits since communication to the outside
world is through either an 8-bit I2C interface or a 1-bit
single-wire interface. Writing a single byte to any
address location is ignored.
The 10-bit bus connects together registers, MTP memo-
ries, and digital interfaces. The bus master resides in
the same block as the I2C interface and the single-wire
interface.
VCOM MTP Programming
Through the I2C InterfaceTo program VCOM MTP memory, the I2C master must
first write the DAC code that is to be stored into the
VCOM I2C registers. Next, the I2C master must send a
command to move the data in the VCOM I2C registers
to the VCOM MTP memory, thereby finishing the pro-
gramming.
To read VCOM MTP memory, the I2C master must issue
a command to move the data in the VCOM MTP memo-
ry to the VCOM I2C registers. Then it can read the two
VCOM I2C registers.
To program gamma MTP memory, the I2C master must
first write the complete set of gamma DAC codes into
the gamma I2C registers. For example, six gamma DAC
codes must be written into the MAX9665 since it has six
gamma outputs. Next, the I2C master must send a com-
mand to move the data in the gamma I2C registers to
the gamma MTP memory.
To read gamma MTP memory, the I2C master must
issue a command to move the data in the gamma MTP
memory to the gamma I2C registers. Then it can read
the gamma I2C registers.
During MTP programming, the parts do not respond to
the I2C interface. The part generates an acknowledge
to the MTP programming command, but the I2C inter-
face does not generate further acknowledge signals
until MTP programming is complete.
If the analog supply voltage is not greater than the mini-
mum required for MTP programming, the I2C still
acknowledges the MTP write command, but MTP pro-
gramming is disabled. The I2C continues to acknowl-
edge and process non-MTP write commands.
See the Register Descriptionsection for further expla-
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages VCOM I2C REGISTERS
LOCATION0b0010
VCOM MTP MEMORY
LOCATION0b0011
GAMMA I2C REGISTERS
LOCATION0b0100
GAMMA MTP MEMORY
LOCATION0b0101
BUS MASTER
I2C INTERFACE
SINGLE-WIRE INTERFACE
10-BIT BUS
VCOM WINDOW
MTP MEMORY
LOCATION0b0001
VCOM WINDOW
REGISTERS
LOCATION0b0000
Figure 3. 10-Bit Bus
MAX9665/MAX9666/MAX9667
Through the Single-Wire InterfaceFor VCOM MTP programming through the single-wire
interface, see the Single-Wire Interfacesection.
VCOM Programming RangeTwo registers, VCOMMIN and VCOMMAX, are provided
to set the minimum and maximum VCOM register value.
These two registers are accessed through the I2C inter-
face and can be written to and read from MTP memory.
If any adjustment, either through I2C or the single-wire
interface takes the VCOM register value less than
VCOMMIN, then the value in VCOMMIN is stored in the
VCOM register. Similarly, if any adjustment, either
through I2C or the single-wire interface takes the VCOM
register value greater than VCOMMAX, then the value
in VCOMMAX is stored in the VCOM register.
I2C InterfaceThe MAX9665/MAX9666/MAX9667 feature an I2C/
SMBus™-compatible, 2-wire serial interface consisting
of a serial-data line (SDA) and a serial-clock line (SCL).
SDA and SCL facilitate communication between the
devices and the master at clock rates up to 400kHz.
Figure 4 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the devices by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9665/MAX9666/MAX9667 is
8 bits long and followed by an acknowledge clock
pulse. A master reading data from the devices transmits
the proper slave address followed by a series of nine
SCL pulses. The devices transmit data on SDA in sync
with the master-generated SCL pulses. The master
acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on the SDA bus. SCL operates as only an
input. A pullup resistor, typically greater than 500Ω, is
required on SCL if there are multiple masters on the bus,
or if the master in a single-master system has an open-
drain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the devices from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit TransferOne data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the2C bus is not busy.
START and STOP ConditionsSDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 5). A
START condition from the master signals the beginning
of a transmission to the MAX9665/MAX9666/MAX9667.
The master terminates transmission, and frees the bus,
by issuing a STOP condition. The bus remains active if
a REPEATED START condition is generated instead of
a STOP condition.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference VoltagesSCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD,STA
tSU,STA
tHD,STAtSP
tBUF
tSU,STOtLOW
tSU,DAT
tHD,DAT
tHIGHtF
Figure 4. I2C Serial-Interface Timing Diagram
Early STOP ConditionsThe MAX9665/MAX9666/MAX9667 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
Slave AddressThe slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/Wbit to 1 to configure the MAX9665/MAX9666/
MAX9667 to read mode. Set the R/Wbit to 0 to config-
ure the MAX9665/MAX9666/MAX9667 to write mode.
The address is the first byte of information sent to the
MAX9665/MAX9666/MAX9667 after the START condi-
tion. The MAX9665/MAX9666/MAX9667 slave address
is 0x9E for writing and 0x9F for reading.
AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that the
MAX9665/MAX9666/MAX9667 use to handshake
receipt of each byte of data when in write mode (see
Figure 6). The MAX9665/MAX9666/MAX9667 pull down
SDA during the entire master-generated ninth clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9665/
MAX9666/MAX9667 are in read mode. An acknowledge
is sent by the master after each read byte to allow data
transfer to continue. A not acknowledge is sent when
the master reads the final byte of data from the
MAX9665/MAX9666/MAX9667, followed by a STOP
condition.
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference VoltagesSCL
SDA
SSrP
Figure 5. START, STOP, and REPEATED START ConditionsSCL
START
CONDITION
SDA9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 6. Acknowledge
B6B5B4B3B2B1B0WRITE ADDRESS
(hex)
READ ADDRESS
(hex)1001111R/W0x9E0x9F
Table 2. Slave ID Description
MAX9665/MAX9666/MAX9667
Write Data FormatA write to the MAX9665/MAX9666/MAX9667 consists of
transmitting a START condition, the slave address with
the R/Wbit set to 0, one data byte of data to configure
the internal register address pointer, one or more data
bytes, and a STOP condition. Figure 7 illustrates the
frame format for writing one byte of data to the
MAX9665/MAX9666/MAX9667.
The slave address with the R/Wbit set to 0 indicates
that the master intends to write data to the MAX9665/
MAX9666/MAX9667. The MAX9665/MAX9666/MAX9667
acknowledge receipt of the address byte during the mas-
ter-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9665/MAX9666/MAX9667’s internal reg-
ister address pointer. The pointer tells the MAX9665/
MAX9666/MAX9667 where to write the next byte of
data. An acknowledge pulse is sent by the MAX9665/
MAX9666/MAX9667 upon receipt of the address
pointer data.
The third byte sent to the MAX9665/MAX9666/MAX9667
contains the data that is written to the chosen register.
An acknowledge pulse from the MAX9665/MAX9666/
MAX9667 signals receipt of the data byte. The address
pointer autoincrements to the next register address
after each received data byte. This autoincrement fea-
ture allows a master to write to sequential register
address locations within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition.
Read Data FormatThe master presets the address pointer by first sending
the MAX9665/MAX9666/MAX9667’s slave address with
the R/Wbit set to 0 followed by the register address
after a START condition. The MAX9665/MAX9666/
MAX9667 acknowledge receipt of the slave address
and the register address by pulling SDA low during the
ninth SCL clock pulse. A REPEATED START condition
is then sent followed by the slave address with the R/W
bit set to 1. The MAX9665/MAX9666/MAX9667 transmit
the contents of the specified register. Transmitted data
is valid on the rising edge of the master-generated seri-
al clock (SCL). The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from the register address
location set by the previous transaction and not 0x00
and subsequent reads autoincrement the address
pointer until the next STOP condition. Attempting to
read from register addresses higher than the highest
valid address locations (0x13 for MAX9665, 0x17 for
MAX9666, 0x1B for MAX9667) in repeated reads from a
dummy register containing all one data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 8
and 9 illustrate the frame format for reading data from
the MAX9665/MAX9666/MAX9667.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages0SLAVE ADDRESSREGISTER ADDRESSDATA BYTE
ACKNOWLEDGE FROM MAX9665–MAX9667
R/W1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9665–MAX9667
ACKNOWLEDGE FROM MAX9665–MAX9667B0B3B2B5B4B7B6AAP
Figure 7. Writing One Byte of Data to the MAX9665/MAX9666/MAX9667
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
1 BYTE
AUTO-INCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
NOT ACKNOWLEDGE FROM MASTERAPA0
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
R/WR/W
REPEATED START1SLAVE ADDRESSREGISTER ADDRESSSLAVE ADDRESS DATA BYTE
Figure 8. Reading One Indexed Byte of Data from the MAX9665/MAX9666/MAX9667
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
ACKNOWLEDGE FROM MASTERB0B3B2B5B4B7B6AA0
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
R/WA
1 BYTE
NOT ACKNOWLEDGE FROM MASTERB0B3B2B5B4B7B6ASLAVE ADDRESSREGISTER ADDRESSDATA BYTE 1 DATA BYTE n
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
R/W1SLAVE ADDRESS
REPEATED START
Figure 9. Reading n Bytes of Indexed Data from the MAX9665/MAX9666/MAX9667
MAX9665/MAX9666/MAX9667
Register MapThe I2C interface was architected for 8-bit systems.
With the increase in DAC resolution from 8 bits to 10
bits, 2 bytes must be transferred to get 10 bits.
Therefore, the word size is 2 bytes (16 bits) in the regis-
ter map. Byte order is big endian. The least significant
byte (LSB) holds the bottom 8 bits of the 10-bit data,
while the most significant byte (MSB) holds the top 2
bits of the 10-bit data. The I2C stores each 10-bit DAC
code in two 8-bit registers, as shown in the register
maps of Tables 3, 4, and 5.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
LEAST SIGNIFICANT BYTEMOST SIGNIFICANT BYTE
REGISTER
ADDRESSREGISTER NAMEREGISTER
ADDRESSREGISTER NAMECOMMENTS0x01CMD_OPND0x00CMD_OPRNCommand
0x03VCOMMIN_L0x02VCOMMIN_MVCOM (minimum)
0x05VCOMMAX_L0x04VCOMMAX_MVCOM (maximum)
0x07VCOM_L0x06VCOM_MVCOM
0x09GMA0_L0x08GMA0_MGamma 0
0x0BGMA1_L0x0AGMA1_MGamma 1
0x0DGMA2_L0x0CGMA2_MGamma 2
0x0FGMA3_L0x0EGMA3_MGamma 3
0x11GMA4_L0x10GMA4_MGamma 4
0x13GMA5_L0x12GMA5_MGamma 5
Table 3. Register Map for MAX9665
LEAST SIGNIFICANT BYTEMOST SIGNIFICANT BYTE
REGISTER
ADDRESSREGISTER NAMEREGISTER
ADDRESSREGISTER NAMECOMMENTS0x01CMD_OPND0x00CMD_OPRNCommand
0x03VCOMMIN_L0x02VCOMMIN_MVCOM (minimum)
0x05VCOMMAX_L0x04VCOMMAX_MVCOM (maximum)
0x07VCOM_L0x06VCOM_MVCOM
0x09GMA0_L0x08GMA0_MGamma 0
0x0BGMA1_L0x0AGMA1_MGamma 1
0x0DGMA2_L0x0CGMA2_MGamma 2
0x0FGMA3_L0x0EGMA3_MGamma 3
0x11GMA4_L0x10GMA4_MGamma 4
0x13GMA5_L0x12GMA5_MGamma 5
0x15GMA6_L0x14GMA6_MGamma 6
0x17GMA7_L0x16GMA7_MGamma 7
Table 4. Register Map for MAX9666
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
LEAST SIGNIFICANT BYTEMOST SIGNIFICANT BYTE
REGISTER
ADDRESSREGISTER NAMEREGISTER
ADDRESSREGISTER NAMECOMMENTS0x01CMD_OPND0x00CMD_OPRNCommand
0x03VCOMMIN_L0x02VCOMMIN_MVCOM (minimum)
0x05VCOMMAX_L0x04VCOMMAX_MVCOM (maximum)
0x07VCOM_L0x06VCOM_MVCOM
0x09GMA0_L0x08GMA0_MGamma 0
0x0BGMA1_L0x0AGMA1_MGamma 1
0x0DGMA2_L0x0CGMA2_MGamma 2
0x0FGMA3_L0x0EGMA3_MGamma 3
0x11GMA4_L0x10GMA4_MGamma 4
0x13GMA5_L0x12GMA5_MGamma 5
0x15GMA6_L0x14GMA6_MGamma 6
0x17GMA7_L0x16GMA7_MGamma 7
0x19GMA8_L0x18GMA8_MGamma 8
0x1BGMA9_L0x1AGMA9_MGamma 9
Table 5. Register Map for MAX9667
Register DescriptionThe I2C registers either hold DAC codes or commands
(see Tables 6, 7, and 8). After power-up, the digital cir-
cuitry loads the values stored in MTP memory into the
VCOM and gamma registers. This process takes
approximately 350µs. During this time, the I2C does not
respond to any commands (either from the user or from
the single-wire interface). To ensure the gamma chip
does not reverse bias, the source driver, the VCOM
DAC code, and the gamma DAC codes upon power-up
are as shown in the Tables 6, 7, and 8.
The I2C master can write a command such as MOV
(move) into a pair of command registers. To execute a
valid command, the command operation (CMD_OPRN)
and command operand (CMD_OPND) registers must
be written to sequentially in the same I2C transaction
(between the same I2C start/stop).
The form of the command is shown below:
To move data from gamma registers to gamma MTP
memory, use the following command (essentially, data
is being written into MTP memory):
MOV is the operation. Gamma registers and gamma
MTP memory are operands. Both the operation and the
operands must be assembled into machine code that is
written into the command registers. The machine code
for the operation must be written into the command
operation register (CMD_OPRN). The machine code for
the operands (if there are any) must be written into
command operand register (CMD_OPND). Table 9
shows the list of operations and operands.
OperationOperands
MOVMOV Gamma RegistersGamma MTP
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
BITREGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION6543210
POWER-ON
RESET
VALUE
MTP FACTORY
INITIALIZATION
VALUE
READ
AND
WRITE0x00CMD_OPRNCommand
operationd7d6d5d4d3d2d1d00x00Not applicableWrite
only
0x01CMD_OPNDCommand
operandd7d6d5d4d3d2d1d00x00Not applicableWrite
only
0x02VCOMMIN_M
VCOMMIN
(most significant
byte)xxxxxd9d80x000x00
Read
and
write
0x03VCOMMIN_L
VCOMMIN
(least significant
byte)d6d5d4d3d2d1d00x000x00
Read
and
write
0x04VCOMMAX_M
VCOMMAX
(most significant
byte)xxxxxd9d80x030x03
Read
and
write
0x05VCOMMAX_L
VCOMMAX
(least significant
byte)d6d5d4d3d2d1d00xFF0xFF
Read
and
write
0x06VCOM_MVCOM (most
significant byte)xxxxxxd9d80x020x02
Read
and
write
0x07VCOM_LVCOM (least
significant byte)d7d6d5d4d3d2d1d00x000x00
Read
and
write
0x08GMA0_M
Gamma 0
(most significant
byte)xxxxxd9d80x030x03
Read
and
write
0x09GMA0_L
Gamma 0
(least significant
byte)d6d5d4d3d2d1d00x800x80
Read
and
write
0x0AGMA1_M
Gamma 1
(most significant
byte)xxxxxd9d80x030x03
Read
and
write
0x0BGMA1_L
Gamma 1
(least significant
byte)d6d5d4d3d2d1d00x000x00
Read
and
write
0x0CGMA2_M
Gamma 2
(most significant
byte)xxxxxd9d80x020x02
Read
and
write
Table 6. MAX9665 Register Description
Note:d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
MAX9665/MAX9666/MAX9667
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
BITREGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION76543210
POWER-ON
RESET
VALUE
MTP FACTORY
INITIALIZATION
VALUE
READ
AND
WRITE0x0DGMA2_L
Gamma 2
(least significant
byte)d6d5d4d3d2d1d00x800x80
Read
and
write
0x0EGMA3_M
Gamma 3
(most significant
byte)xxxxxd9d80x010x01
Read
and
write
0x0FGMA3_L
Gamma 3
(least significant
byte)d6d5d4d3d2d1d00x800x80
Read
and
write
0x10GMA4_M
Gamma 4
(most significant
byte)xxxxxd9d80x010x01
Read
and
write
0x11GMA4_L
Gamma 4
(least significant
byte)d6d5d4d3d2d1d00x000x00
Read
and
write
0x12GMA5_M
Gamma 5
(most significant
byte)xxxxxd9d80x000x00
Read
and
write
0x13GMA5_L
Gamma 5
(least significant
byte)d6d5d4d3d2d1d00x800x80
Read
and
write
Table 6. MAX9665 Register Description (continued)
Note:d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
