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MAX9590ETU+-MAX9590ETU+T
14 Programmable Gamma Reference Buffers with 4 Static References for TFT-LCD Displays
MAX9590
14 Programmable Gamma Reference Buffers with
FourStatic References for TFT-LCD Displays
Ordering Information19-0551; Rev 1; 7/06
+Denotes lead-free package.
**EP = Exposed paddle.
PARTTEMP RANGEPIN-PACKAGEPKG
CODEMAX9590ETU+-40°C to +85°C38 TQFN-EP**
(5mm x 7mm)T3857-1
I2C INTERFACE
REFU_H
BANK_SEL
REFL_L
SCL
SDA
REFU_L
REFL_H
AVDD
DVDD
GND
BANK A
MEMORY
(HIGH)
OUT_REFU_H
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT_REFU_L
OUT_REFL_H
OUT_REFL_L
STD_REG
CAP
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
BANK B
MEMORY
(HIGH)
BANK A
MEMORY
(LOW)
BANK B
MEMORY
(LOW)
MAX9590
Block Diagram
14 Programmable Reference Voltages
Four Static Reference Voltages
Independent DACs with 8-Bit Resolution
Two Register Banks for Two Sets of
Gamma Values
Fast Switching between Gamma Values
16.5V (max) Operating Voltage
Output Swing within 150mV of Rails
Peak Current Greater than 200mA
Output Channels Tri-Stated During Wake-Up
General DescriptionThe MAX9590 provides 14 programmable voltage
references and four static voltage references for
gamma correction in TFT-LCD displays. Two register
banks are provided to store two sets of gamma refer-
ence values. Gamma values are programmed into the
banks through the I2C interface and the outputs can
switch between values in 0.5µs.
The 14 programmable reference voltages are divided
evenly into seven upper and seven lower voltages for the
upper and lower gamma curves of LCD column drivers.
Each gamma reference voltage has an 8-bit digital-to-
analog converter (DAC) and isolation buffer associated
with it to ensure stable operation.Therefore, the refer-
ence voltages remain stable without synchronizing to the
LCD horizontal timing. In addition, each buffer is able to
provide a high current that further ensures a stable volt-
age when critical levels and patterns are displayed.
The 14 programmable buffers wake up in the high-imped-
ancestate until the registers are programmed. This pro-
tects the LCD system from high transient currents
during the startup phase.
The MAX9590 is available in a 38-pin TQFN package
and is specified for operation over the -40°C to +85°C
temperature range.
TFT-LCD Displays
Industrial Reference Voltage Generators
Applications
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= 15V, DVDD= 3.3V, VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V, VREFL_L= 1V, GND = 0V, no load. TA= -40°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto GND..........................................................-0.3V to +18V
DVDDto GND...........................................................-0.3V to +6V
REFU_H, REFU_L, REFL_H, REFL_L.......-0.3V to (AVDD+ 0.3V)
OUT1–OUT14...........................................-0.3V to (AVDD+ 0.3V)
OUT_REFU_H, OUT_REFU_L,
OUT_REFL_H, OUT_REFL_L...............-0.3V to (AVDD+ 0.3V)
STD_REG, A0, SDA, SCL, BANK_SEL, CAP to GND....-0.3V to +6V
Continuous Current
SDA.................................................................................50mA
CAP.................................................................................20mA
OUT1–OUT14................................................................400mA
OUT_REFU_H, OUT_REFU_L,
OUT_REFL_H, OUT_REFL_L........................................400mA
Short-Circuit Duration
Any Output to AVDDor GND..................................Continuous
Continuous Power Dissipation (TA= +70°C)
38-Pin TQFN (derate 26.3mW/°C above +70°C) ......2195mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................-65°C to +150°C
Lead Temperature (soldering, 10s) ...............................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLIESAnalog Supply Voltage RangeAVDDGuaranteed by power-supply rejection ratio
specification9.016.5V
Digital Supply Voltage RangeDVDD2.75.5V
Analog Quiescent CurrentIAVDD2132mA
Undervoltage Lockout ThresholdUVLODVDD undervoltage lockout threshold1.5V
During a register mode load event200Digital Quiescent CurrentIDVDDNo SCL or SDA transitions46100µA
HIGH REFERENCE BUFFERS (REFU_H, REFL_H)Output Voltage RangeVOUTTA = +25°C, sinking or sourcing 4mA3.0AVDD - 0.15V
Input Voltage RangeVCMTA = +25°C, sinking or sourcing 4mA3.0AVDDV
Offset VoltageVOSVOUT = 5V110mV
Input ResistanceRIN100MΩ
Load RegulationREG-12mA to +12mA0.25mV/mA
Power-Supply Rejection RatioPSRR9V ≤ AV D D ≤ 16.5V , outp uts at 5V 6090dB
Short-Circuit CurrentISCTo AVDD or GND400mA
Slew RateSRSwing 5VP-P at input, 10% to 90%
measurement on output10V/µs
LOW REFERENCE BUFFERS (REFU_L, REFL_L)Output-Voltage RangeVOUTTA = +25°C, sinking or sourcing 4mAGND + 0.15 AVDD - 3.7V
Input-Voltage RangeVCMTA = +25°C, sinking or sourcing 4mAGND AVDD - 3.7V
Offset VoltageVOSVOUT = 5V110mV
Input ResistanceRIN100MΩ
Load RegulationREG-12mA to +12mA0.25mV/mA
Power-Supply Rejection RatioPSRR9V ≤ AV D D ≤ 16.5V , outp uts at 5V 6090dB
Short-Circuit CurrentISCTo AVDD or GND400mA
Slew RateSRSwing 5VP-P at input, 10% to 90%10V/µs
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 15V, DVDD= 3.3V, VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V, VREFL_L= 1V, GND = 0V, no load. TA
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONS
DAC OUTPUTS (OUT1–OUT14)ResolutionRESLinear
Integral Nonlinearity ErrorINL0.5LSB
Differential Nonlinearity ErrorDNL0.25LSB
Full-Scale ErrorEFS0.5LSB
Zero-Code ErrorEZC0.5LSB
Output-Voltage RangeVOUTTA = +25°C, sinking or sourcing 4mA0.15AVDD - 0.15V
Load Regulation-12mA to +12mA0.50mV/mA
Power-Supply Rejection RatioPSRR9V ≤ AV D D ≤ 16.5V , outp uts at 5V 6090dB
ISC1Outputs 1, 7, 8, 14 to AVDD or GND400Short-Circuit CurrentISC2All other outputs to AVDD or GND200mA
Output ImpedanceZOOutput resistance of voltage source when
buffer disabled100kΩ
Slew RateSRSwing 5VP-P at input, 10% to 90%
measurement on OUT1–OUT1422V/µs
Settling Time
OUT1–OUT14 swing 5VP-P, and settled to
±0.5 LSB, switch from Bank A to Bank B or
vice versa, RL = 10kΩ to GND and CL =
50pF to GND (Note 2)
0.5µs
Channel-to-Channel IsolationCXTLKf = 5MHz, all channels to all channels80dB
NoiseEnRMS noise voltage at any output
(10MHz BW)375µV
Thermal ShutdownTs+160°C
Thermal Shutdown HysteresisHys15°C
LOGIC INPUTS AND OUTPUTS (SDA, SCL, BANK_SEL, STD_REG, A0)Input High VoltageVIH2.2V
Input Low VoltageVIL0.8V
Input Leakage CurrentIIH, IILVIN = 0V or DVDD-1+0.01+1µA
Input CapacitanceGuaranteed by design, not subject to
production testing5pF
Power-Down Input CurrentIINDVDD = 0V, VIN = 1.98V (Note 3)-10+10µA
SDA Output Low VoltageVOLISINK = 6mA0.4V
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
Note 1:All devices are 100% productiontested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 2:Reference voltages transition from Bank A to Bank B value in less than 500ns. The Timing Diagramshows the response at
the output pin.
Note 3:Only SCL and SDA are high impedance.
ELECTRICAL CHARACTERISTICS (continued)(AVDD= 15V, DVDD= 3.3V, VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V, VREFL_L= 1V, GND = 0V, no load. TA= -40°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS2C TIMING CHARACTERISTICS (Figure 1)Serial Clock FrequencyfSCL0400kHz
Bus Free Time Between STOP (P)
and START (S) ConditiontBUF1.3µs
Hold Time (Repeated) START (S)
ConditiontHD,STA0.6µs
SCL Pulse-Width LowtLOW1.3µs
SCL Pulse-Width HightHIGH0.6µs
Setup Time for a Repeated START
ConditiontSU,STA0.6µs
Data Hold TimetHD,DAT
A m aster d evi ce m ust p r ovi d e a hol d ti m e of ateast 300ns for the S D A si g nal ( r efer r ed to V IL
of the S C L si g nal ) to b r i d g e the und efi ned eg i on of S C L’ s fal l i ng ed g e0.9µs
Data Setup TimetSU,DAT100ns
Setup Time for STOP ConditiontSU,STO0.6µs
Pulse Width of Suppressed SpiketSP
Guaranteed by design, input filters on the
SDA and SCL inputs suppress noise spikes
less than 50nsns
±0.5 LSB
BANK_SEL
OUT_< 0.5μs
Timing Diagram
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
INPUT OFFSET VOLTAGE DEVIATION
vs. SUPPLY VOLTAGEMAX9590 toc01
AVDD (V)
(mV)141012
INPUT OFFSET VOLTAGE DEVIATION
vs. TEMPERATURE
MAX9590 toc02
TEMPERATURE (°C)
(mV)50-25025
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX9590 toc03
AVDD (V)
IAVDD
(mA)141012
NO LOAD
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX9590 toc04
DVDD (V)
IDVDD34
LOGIC INPUTS = DVDD OR 0
SETTLING TIMEMAX9590 toc05a
100ns/div
OUT
500mV/div
BANK_SEL
1V/div
OUT IS SWITCHING FROM 2V TO 5V. OUT IS
SETTLING TIMEMAX9590 toc05b
100ns/div
OUT
500mV/div
OUT IS SWITCHING FROM 5V TO 2V. OUT IS
BANK_SEL
1V/div
Typical Operating Characteristics(AVDD= 15V, DVDD= 3.3V, VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V, VREFL_L= 1V, GND = 0V, no load. TA
otherwise noted.)
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
Typical Operating Characteristics (continued)(AVDD= 15V, DVDD= 3.3V, VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V, VREFL_L= 1V, GND = 0V, no load. TA= +25°C, unless
otherwise noted.)
LOAD REGULATIONMAX9590 toc06a
ILOAD (mA)
OUTPUT VOLTAGE (V)-20-102010
OUT_REFU_H
OUT_ AT MIDCODE
OUT_REFU_L
OUT_REFL_L
OUT_REFL_H
OUT_ AT MIDCODE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODEMAX9590 toc07
DIGITAL INPUT CODE
INL (LSB)
LOAD REGULATION
MAX9590 toc06b
ILOAD (mA)
OUTPUT VOLTAGE (V)-12-881240
OUT_ AT MIDCODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODEMAX9590 toc08
DIGITAL INPUT CODE
DNL (LSB)
-0.10255
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
PINNAMEFUNCTIONOUT_REFU_HREFU_H Buffered Output
2, 21AVDDAnalog Power Supply. Bypass to GND with 0.1µF and 10µF capacitors.STD_REGOperation Mode Select. Input that selects mode of operation. Set STD_REG = 0 to select
register mode. Set STD_REG = 1 to select standard mode. See the I2C Compatibility section.
4A0I2C Slave ID Selector Input. Connect to SCL or SDA or DVDD or GND.SDAI2C-Compatible Serial Data Input/OutputSCLI2C-Compatible Serial Clock
7, 10, 24, 25N.C.No Connection. Not internally connected. Leave unconnected.
8DVDDDigital Power Supply. Bypass to GND with a 0.1µF capacitor.BANK_SELBank Select. Logic input that selects the set of reference voltages buffered to the outputs. Set
BANK_SEL = 0 to select Bank A. Set BANK_SEL = 1 to select Bank B.
11, 28, 30GNDGroundOUT_REFL_LREFL_L Buffered OutputOUT14Lower DAC Analog Output 14OUT13Lower DAC Analog Output 13OUT12Lower DAC Analog Output 12OUT11Lower DAC Analog Output 11OUT10Lower DAC Analog Output 10OUT9Lower DAC Analog Output 9OUT8Lower DAC Analog Output 8OUT_REFL_HREFL_H Buffered OutputREFU_HUpper DAC High Reference Voltage InputREFU_LUpper DAC Low Reference Voltage InputREFL_HLower DAC High Reference Voltage InputREFL_LLower DAC Low Reference Voltage InputCAPInternal Voltage Reference. Bypass to GND with a 0.1µF capacitor (10V). Do not connect
external loads.OUT_REFU_LREFU_L Buffered OutputOUT7Upper DAC Analog Output 7OUT6Upper DAC Analog Output 6OUT5Upper DAC Analog Output 5OUT4Upper DAC Analog Output 4OUT3Upper DAC Analog Output 3OUT2Upper DAC Analog Output 2OUT1Upper DAC Analog Output 1
—EPExposed Paddle. Internally connected to ground. Leave EP unconnected or connect the EP to
the ground plane for improved thermal conductivity.
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
Functional DiagramI2C INTERFACE
REFU_H
BANK_SEL
REFL_L
SCL
SDA
REFU_L
REFL_H
AVDD
DVDD
GND
BANK A
MEMORY
(HIGH)
OUT_REFU_H
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT_REFU_L
OUT_REFL_H
OUT_REFL_L
STD_REG
CAP
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
BANK A
MEMORY
(LOW)
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
BANK B
MEMORY
(LOW)
MAX9590
BANK B
MEMORY
(HIGH)
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD DisplaysAVDD
REFU_H
REFU_L
REFL_H
REFL_L
OUT_REFL_L
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT_REFU_H
OUT_REFU_L
OUT_REFL_H
TFT-LCD
COLUMN DRIVER
V10
V11
V12
V13
V14
V15
V16
V17
V18
9V TO 16.5V
GND
0.1μF10μF
CAP
0.1μF2C INTERFACE
SCL
SDA
A0*
*ADDRESS SHOWN SET UP FOR OxE8/OxE9
STD_REG
0.1μF
DVDD
BANK_SEL
MAX9590
ypical Application Circuit
MAX9590
14 Programmable Gamma Reference Buffers with
Four Static References for TFT-LCD Displays
Detailed Description
The MAX9590 provides 14 channels of programmable
voltage references and four channels of static voltage
references for gamma correction in TFT-LCD displays.
Two register banks are provided to store two different
sets of gamma reference values. Gamma values are
programmed into the banks through the I2C interface
and the outputs can switch between values in 0.5µs.
Output Buffers
The 14 programmable reference voltages are divided
evenly into seven upper and seven lower voltages for the
upper and lower gamma curves of LCD column drivers.
The seven upper voltages cover the range between
REFU_L to REFU_H. The seven lower voltages cover
the range of REFL_L to REFL_H.
Each gamma reference voltage has an 8-bit DAC and
isolation buffer associated with it to ensure stable
operation. Therefore, the reference voltages remain
stable without synchronization to the LCD horizontal
timing. In addition, each buffer is able to provide a high
current that further ensures a stable voltage when
critical levels and patterns are displayed.
Each of the MAX9590 output buffers hold the reference
voltages stable while providing the ability to source and
sink current (200mA) into a capacitive load such as
LCD column drivers. When switching from Bank A to
Bank B or vice versa, the outputs settle to within ±0.5
LSB in less than 0.5µs.
8-Bit DAC
Each voltage is generated by an 8-bit DAC and
programmed values are set through the I2C interface.
The input code data is used to set the output voltages
of the MAX9590. See the I2C Compatibilitysection.
The ideal transfer function of the upper reference
voltages is:
while the ideal transfer function of the lower reference
voltages is:
D = 27 (B7) + 26 (B6) + 25 (B5) + 24 (B4) + 23(B3)
+ 22 (B2) + 21 (B1) + 20 (B0)
D is the decimal value of the input binary code. B7 is the
most significant bit of the data byte and is clocked in first.
Table1 shows the ideal output voltage of VOUT1and
VOUT14with the following typical conditions:
VREFU_H= 14V, VREFU_L= 9V, VREFL_H= 6V,
and VREFL_L= 1V
Register Banks
The MAX9590 features two register banks: Bank A and
Bank B. The user can program one set of gamma
values into Bank A while Bank B is being used to drive
the LCD column drivers and vice versa.
Set BANK_SEL = 0 to select Bank A and set
BANK_SEL = 1 to select Bank B. The gamma voltage
transition from Bank A to Bank B and vice versa takes
place in less than 500ns. See the Register Address
section for details on memory bank internal registers.
Power-On Reset (POR)
The MAX9590 contains an integrated POR circuit that
ensures all registers are reset to a zero state on power-up.
Once DVDDrises above 1.5V (typ), the POR circuit releas-
es the registers for normal operation. Should the DVDD
input drop to less than 1.5V (typ), the POR is activated.
After a POR, the outputs (OUT1–OUT14) are in high-
impedance mode until a minimum of two data byteshave
been written to bothBank A and Bank B in any order.VtoVVDVVOUTOUTREFLLREFLHREFLL814255 ()___=+×−
VtoVVDVVOUTOUTREFULREFUHREFUL12255 ()___=+×−
Table1. Ideal Output Voltage with Typical
Conditions
BINARY
INPUT
DECIMAL
VALUE
VOUT1
(V)
VOUT14
(V)
0000 000009.001.00
0000 000119.0191.019
0000 001139.0581.058
0000 011179.1361.136
0000 1111159.2921.292
0001 1111319.6051.605
0011 11116310.2302.230
0111 111112711.4803.480
1111 111125514.006.00
