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MAX9486EUGMAXIMN/a9avai8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz


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MAX9486EUG
8kHz Reference Clock Synthesizer with Multiple Outputs at 35.328MHz
General Description
The MAX9486 low-cost, high-performance clock syn-
thesizer with an 8kHz input reference clock provides six
buffered LVTTL clock outputs at 35.328MHz. The clock
synthesizer can be used to generate the clocks for T1,
E1, T3, E3, and xDSL.
The MAX9486 has two phase-lock loops (PLLs). The
first PLL uses a voltage-controlled crystal oscillator
(VCXO). The second PLL is a frequency multiplier. With
the two PLLs, the MAX9486 generates the output fre-
quency at 35.328MHz. In addition, this device gener-
ates a jitter-suppressed 8kHz output that provides a
better source for the reference clock relay.
The MAX9486 is available in a 24-pin TSSOP package
and operates over the extended operating temperature
range of -40°C to +85°C and a single +3V to +3.6V
power-supply range.
Applications

Telecom Equipment Using T1, E1, T3, E3, and
ISDN Protocols
xDSL Equipment in CO with Interface to the
Telecom Protocols
Features
8kHz Input Reference CLKHigh-Jitter Rejection on the Reference CLKSynthesizer Locks to the 8kHz Reference with a
±200ppm Range
Output Frequency: 35.328MHzSix Buffered LVTTL Low-Jitter OutputsOne 8kHz Reference CLK Relay Output+3.3V Supply Operation24-Pin TSSOP Package
MAX9486
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
Ordering Information
Pin Configuration
Typical Application Circuit
MAX9486
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VDD= VDDP= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= VDDP= +3.3V, TA=
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +4.0V
VDDPto GNDP.......................................................-0.3V to +4.0V
SHDN, REO, REIN, X1, X2, CLK_ to GND...-0.3V to (VDD+ 0.3V)
LP1, SETI to GNDP.....................................-0.3V to (VDD+ 0.3V)
LP2 Internally Connected to GNDP
Short-Circuit Duration of Outputs...............................Continuous
Continuous Power Dissipation (TA= +70°C)
24-Pin TSSOP (derate 12.2mW/°C above +70°C).......976mW
Operating Temperature Range...........................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
ESD Rating (Human Body Model).......................................±2kV
Lead Temperature (soldering, 10s).................................+300°C
MAX9486
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
Note 2:
No load on clock outputs.
Note 3:
Guaranteed by design.
Note 4:
Crystal loading capacitance is 14pF.
AC ELECTRICAL CHARACTERISTICS

(VDD= VDDP= +3.0V to +3.6V, CL= 20pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= VDDP= +3.3V,
MAX9486
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
Typical Operating Characteristics

(VDD= VDDP= +3.3V, TA= +25°C, unless otherwise noted.)
MAX9486
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
MAX9486
Detailed Description

The MAX9486 is a high-performance clock synthesizer
with an 8kHz input reference clock. This device gener-
ates six identical buffered LVTTL clock outputs at
35.328MHz. The MAX9486 features two PLLs. The first
PLL (PLL1) uses an internal VCXO, locked to the 8kHz
reference CLK, to generate a 17.664MHz CLK output
for the second PLL (PLL2). PLL2 multiplies the VCXO
frequency by a factor of 2 to produce the 35.328MHz
outputs. In addition, this device features a low-jitter
8kHz output that provides a better source for the refer-
ence clock relay (see the Functional Diagram).
Power-Up

At power-up, all the outputs are disabled and pulled
low (to GND) for at least 256ms. After 256ms, the crys-
tal oscillator starts oscillation. The input reference clock
for PLL1 is 8kHz and its output frequency, 17.664MHz,
is also the reference clock for PLL2. If the 8kHz refer-
ence clock is not present at power-up, the output fre-
quency of PLL1 is locked to the center frequency of the
crystal oscillator.
8kHz Reference CLK Monitor

The MAX9486 features an internal clock (CLK) monitor
circuitry to detect the presence of the external 8kHz ref-
erence clock. The internal CLK monitor continuously
monitors the number of low-to-high transitions within a
three-cycle (at 8kHz) time window. If the transition num-
ber is less than two, the internal CLK monitor states
loss of the reference CLK. However, if in a three-cycle
time window the monitor counts two or three transitions,
it considers the input reference clock as present. When
the monitor detects the absence of the 8kHz reference
clock, PLL2 is forced to lock to the crystal oscillator fre-
quency. However, when the monitor detects the return
of the reference clock, PLL1 locks to the reference
clock again.
Clock Outputs (CLK1 to CLK6) and REO

The MAX9486 uses a 17.664MHz crystal and a refer-
ence clock (REIN) to generate six identical outputs,
CLK1 to CLK6, at 35.328MHz. All CLK_ outputs are
LVTTL with a skew of 185ps. The MAX9486 also regen-
erates the 8kHz reference CLK at REO output.
Voltage-Controlled Crystal
Oscillator (VCXO)

The MAX9486’s internal VCXO takes an external
17.664MHz crystal as the base frequency and has a
pulling range of approximately ±200ppm. This configu-
ration also makes the VCXO PLL become a narrowband
filter to reject high-frequency jitter on the input reference
and eliminate it from the REO and CLK_ outputs.
8kHz Reference Clock Synthesizer
with Multiple Outputs at 35.328MHz
Functional Diagram
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