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MAX9380ESAMAXIMN/a211avaiSingle-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
MAX9380EUAMAXN/a10avaiSingle-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer


MAX9380ESA ,Single-Ended-to-Differential LVECL/LVPECL 2:1 MultiplexerELECTRICAL CHARACTERISTICS(V - V = +3.0V to +3.8V, outputs terminated with 50Ω to V - 2.0V, unless ..
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MAX9380ESA-MAX9380EUA
Single-Ended-to-Differential LVECL/LVPECL 2:1 Multiplexer
General Description
The MAX9380 is a high-speed, low-jitter 2:1 multiplexer
for clock and data distribution applications. The device
selects one of the two single-ended inputs and con-
verts it to a differential output.
The MAX9380 features low part-to-part skew of 33ps
and propagation delay of 263ps.
The MAX9380 operates from a +3.0V to +3.8V supply for
LVPECL applications or from a -3.0V to -3.8V supply for
LVECL applications. The input is selected by a single select
input. The select and data inputs feature internal pulldown
resistors that ensure a low default state if left open.
These devices are specified for operation from -40°C to
+85°C, and are available in space-saving 8-pin µMAX
and SO packages.
Applications

Precision Clock Distribution
DSLAM
DLC
Base Station
ATE
Features
>300mV Differential Output at 3.5GHzLow 20mA Supply Current33ps (typ) Part-to-Part Skew263ps (typ) Propagation Delay<0.2psRMSAdded Random JitterHigh-Speed Select InputOutput Low with Open InputsPin Compatible with MC10EP58
MAX9380
Single-Ended-to-Differential VECL/LVPECL 2:1 Multiplexer
Pin Configuration

19-2236; Rev 0; 10/01
Ordering Information

*Future product—contact factory for availability.
**EP = Exposed paddle.
MAX9380
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +3.0V to +3.8V, outputs terminated with 50Ωto VCC- 2.0V, unless otherwise noted.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................-0.3V to +4.1V
Inputs (Da, Db, SEL).............................VEE- 0.3V to VCC+ 0.3V
Output Current (Continuous)...............................................50mA
Output Current (Surge).....................................................100mA
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin µMAX..............................................................+221°C/W
8-Pin SO*.................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
8-Pin µMAX..............................................................+155°C/W
8-Pin SO*...................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin µMAX................................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (Inputs and Outputs).........................2kV
Soldering Temperature (10s)...........................................+300°C
* Rating is for exposed paddle not connected.
MAX9380
Single-Ended-to-Differential VECL/LVPECL 2:1 Multiplexer
AC ELECTRICAL CHARACTERISTICS

(VCC- VEE= +3.0V to +3.8V, outputs loaded with 50Ωto VCC- 2V, VIH= VCC- 1.11V, VIL= VCC- 1.53V, input frequency = 2.0GHz,
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4:
All pins are open except VCCand VEE.
Note 5:
Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 7:
Device jitter added to the input signal.
MAX9380
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
Typical Operating Characteristics

(VCC- VEE= +3.3V, VIH= VCC- 1.165V, VIL= VCC- 1.475V, outputs loaded with 50Ωto VCC- 2.0V, input frequency = 1GHz, input
transition time = 125ps (20% to 80%), unless otherwise noted.)
MAX9380
Single-Ended-to-Differential VECL/LVPECL 2:1 Multiplexer

Figure 1. Data Input-to-Output Propagation Delay and Transition Timing Diagram
MAX9380
Single-Ended-to-Differential
LVECL/LVPECL 2:1 Multiplexer
Detailed Description

The MAX9380 is a high-speed, low-jitter 2:1 multiplexer
designed for clock and data distribution. The device
selects one of the two single-ended inputs.
The multiplexer function is controlled by the single-
ended SEL input. A high level on the SEL input selects
the single-ended data input Da. Similarly, a low level on
the SEL input selects the single-ended data input Db.
The selected input is converted to a differential signal
at the Q and Qoutputs.
The inputs Da, Db, and SEL have a 75kΩpulldown to
VEE. This ensures that an open input has a low state. All
inputs can be driven from a single-ended LVECL/
LVPECL signal or to VEEand VCC.
Applications Information
LVECL/LVPECL

In LVECL systems, the positive supply voltage is con-
ventionally chosen to be system ground. This arrange-
ment produces the best noise immunity since ground is
normally a system-wide reference voltage. Operate the
MAX9380 with VCC= 0 (ground) and VEE= -3.3V for an
LVECL system.
The MAX9380 operates in LVPECL systems by con-
necting VEEto ground and VCCto a positive supply
voltage. Connect VCC= +3.3V and VEE= 0 for an
LVPECL system.
Power-Supply Bypassing

Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. This is
particularly true of use in an LVPECL system where the
power-supply voltage is used as a reference. Bypass
VCCto VEEwith high-frequency surface-mount ceramic
0.1µF and 0.01µF capacitors in parallel as close to the
device as possible, with the 0.01µF capacitor closest to
the device pins. Use multiple parallel vias for ground
plane connection to minimize inductance.
Circuit Board Traces

Input and output trace characteristics affect the perfor-
mance of ECL devices. Connect each of the MAX9380
inputs and outputs to a 50Ωcharacteristic impedance
trace. Avoid discontinuities in differential impedance
and maximize common-mode noise immunity by main-
taining the distance between differential traces and
avoid sharp corners. Minimize the number of vias to
prevent impedance discontinuities. Reduce reflections
by maintaining the 50Ωcharacteristic impedance
through connectors and across cables. Minimize skew
by matching the electrical length of the traces.
Output Termination

Terminate outputs through 50Ωto VCC- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if the Q output of the MAX9380 is
connected to a single-ended input, terminate both the
Q and Qoutputs.
Figure 2. Select Input-to-Output Propagation Delay and Transition Timing Diagram
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