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MAX9321BESA
Differential PECL/ECL/LVPECL/LVECL Receiver/Driver
General DescriptionThe MAX9321B low-skew differential receiver/driver is
designed for clock and data distribution. The differen-
tial input can be adapted to accept a single-ended
input by connecting the on-chip VBBsupply to an input
as a reference voltage.
The MAX9321B features ultra-low propagation delay
(172ps) and part-to-part skew (20ps) with 24mA maxi-
mum supply current, making this device ideal for clock
buffering or repeating. For interfacing to differential PECL
and LVPECL signals, these devices operate over a +3.0V
to +5.5V supply range, allowing high-performance clock
and data distribution in systems with a nominal 3.3V or
5.0V supply. For differential ECL and LVECL operation,
this device operates from a -3.0V to -5.5V supply.
The MAX9321B is offered in industry-standard 8-pin SO
and TSSOP packages.
ApplicationsPrecision Clock Buffer
Low-Jitter Data Repeater
FeaturesImproved Second Source of the MC10EP16D+3.0V to +5.5V Differential PECL/LVPECL
Operation-3.0V to -5.5V Differential ECL/LVECL OperationLow 17mA Supply Current20ps Part-to-Part Skew172ps Propagation DelayMinimum 300mV Output at 3GHzOutput Low for Open InputESD Protection >2kV (Human Body Model)On-Chip Reference for Single-Ended Input
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
Pin Configuration19-2384; Rev 0; 4/02
Ordering Information*Future product—contact factory for availability.
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC- 2.0V. Typical values are at VCC- VEE= 5.0V, VIHD= VCC- 1V, VILD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto VEE.............................................................................6.0V
D or D...................................................VEE- 0.3V to VCC+ 0.3V
D or Dwith the Other Input Floating....VCC- 5.0V to VCC+ 0.3V
D to D.................................................................................±3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
VBBSink/Source Current.................................................±0.6mA
Continuous Power Dissipation (TA+70°C)
8-Pin TSSOP (derate 4.5mW/°C above +70°C)...........362mW
8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin TSSOP............................................................+221°C/W
8-Pin SO...................................................................+170°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
8-Pin TSSOP............................................................+155°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin TSSOP..............................................................+39°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (D, D, Q_, Q_).................................>2kV
Soldering Temperature (10s)...........................................+300°C
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
DC ELECTRICAL CHARACTERISTICS (continued)(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC- 2.0V. Typical values are at VCC- VEE= 5.0V, VIHD= VCC- 1V, VILD
AC ELECTRICAL CHARACTERISTICS(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC- 2V, input frequency ≤1.5GHz, input transition time = 125ps (20% to
80%), VIHD= VEE+ 1.2V to VCC, VILD= VEEto VCC- 0.15V, VIHD- VILD= 0.15V to 3.0V. Typical values are at VCC- VEE= 5V, VIHD=
VCC- 1V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 7)
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
AC ELECTRICAL CHARACTERISTICS (continued)(VCC- VEE= 3.0V to 5.5V, outputs loaded with 50Ω±1% to VCC- 2V, input frequency ≤1.5GHz, input transition time = 125ps (20% to
80%), VIHD= VEE+ 1.2V to VCC, VILD= VEEto VCC- 0.15V, VIHD- VILD= 0.15V to 3.0V. Typical values are at VCC- VEE= 5V, VIHD=
VCC- 1V, VILD= VCC- 1.5V, unless otherwise noted.) (Notes 1, 7)
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:DC parameters production tested at TA= +25°C. Guaranteed by design and characterization over the full operating temp-
erature range.
Note 4:Maximum differential input voltage limit of ±3V also applies to single-ended use.
Note 5:Use VBBas a reference for inputs on the same device only.
Note 6:All pins open except VCCand VEE.
Note 7:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 9:Device jitter added to the input signal.
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
SUPPLY CURRENT, IEE
vs. TEMPERATUREMAX9321B toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
OUTPUT AMPLITUDE, VOH - VOL
vs. FREQUENCY
MAX9321B toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (V)
TRANSITION TIME vs. TEMPERATURE
MAX9321B toc03
TEMPERATURE (°C)
TRANSITION TIME (ps)3510-15
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT, VIHD
MAX9321B toc04
VIHD (V)
PROPAGATION DELAY (ps)
PROPAGATION DELAY vs. TEMPERATURE
MAX9321B toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)35-1510
Typical Operating Characteristics
(VCC= 5V, VEE= 0V, input transition time = 125ps (20% to 80%), VIHD= VCC- 1V, VILD= VCC- 1.5V, fIN= 1.5GHz, outputs loaded with
50Ωto VCC- 2V, TA= +25°C, unless otherwise noted.)
Detailed DescriptionThe MAX9321B low-skew differential receiver/driver is
designed for clock and data distribution. For interfacing
to differential PECL/LVPECL signals, this device oper-
ates over a +3.0V to +5.5V supply range, allowing high-
performance clock and data distribution in systems with
a nominal 3.3V or 5V supply. For differential ECL/
LVECL operation, this device operates from a -3.0V to
-5.5V supply.
InputsThe differential input can be configured to accept a sin-
gle-ended input. This is accomplished by connecting
the on-chip reference voltage, VBB, to an input as a ref-
erence. For example, the differential input is converted
to a noninverting, single-ended input by connecting
VBBto Dand connecting the single-ended input to D.
An inverting input is obtained by connecting VBBto D
and connecting the single-ended input to D.
When using the VBBreference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBBreference
is not used, it can be left open. The VBBreference can
source or sink 0.5mA. Use VBBonly for an input on the
same device as the VBBreference.
The maximum magnitude of the differential input from D
to Dis 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 50kΩpullup to VCC
and a 100kΩpulldown to VEE.The noninverting input is
biased with an 80kΩpullup to VCC and a 60kΩpull-
down to VEE.
Specifications for the high and low voltage of the differ-
ential input (VIHDand VILD) and the differential input
voltage (VIHD- VILD) apply simultaneously (VILDcannot
be higher than VIHD).
OutputsOutput levels are referenced to VCCand are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the VCCsupply. With VCCconnected to a posi-
tive supply and VEEconnected to GND, the output is
PECL/LVPECL. The output is ECL/LVECL when VCCis
connected to GND and VEEis connected to a negative
supply.
A single-ended input of at least VBB±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the VOHand VOLlevels specified in the DCElectrical
Characteristicstable.
Applications Information
Supply BypassingBypass VCCto VEEwith high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance. When using the VBB
reference output, bypass it with a 0.01µF ceramic
capacitor to VCC(if the VBBreference is not used, it
can be left open).
TracesInput and output trace characteristics affect the perfor-
mance of the MAX9321B. Connect each signal of a differ-
ential input or output to a 50Ωcharacteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ωcharacteristic impedance through connectors and
MAX9321B
Differential PECL/ECL/LVPECL/LVECL
Receiver/Driver
