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MAX9311ECJ+
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
General DescriptionThe MAX9311/MAX9313 are low-skew, 1-to-10 differen-
tial drivers designed for clock and data distribution.
These devices allow selection between two inputs. The
selected input is reproduced at 10 differential outputs.
The differential inputs can be adapted to accept single-
ended inputs by connecting the on-chip VBBsupply to
one input as a reference voltage.
The MAX9311/MAX9313 feature low part-to-part skew
(30ps) and output-to-output skew (12ps), making them
ideal for clock and data distribution across a backplane
or a board. For interfacing to differential HSTL and
LVPECL signals, these devices operate over a +2.25V
to +3.8V supply range, allowing high-performance clock
or data distribution in systems with a nominal +2.5V or
+3.3V supply. For differential LVECL operation, these
devices operate from a -2.25V to -3.8V supply.
The MAX9311 features an on-chip VBBreference output
of 1.425V below the positive supply voltage. The
MAX9313 offers an on-chip VBBreference output of
1.32V below the positive supply voltage.
Both devices are offered in space-saving, 32-pin 5mm ✕
5mm TQFP, 5mm x 5mm QFN, and industry-standard
32-pin 7mm x 7mm LQFP packages.
ApplicationsPrecision Clock Distribution
Low-Jitter Data Repeater
Features+2.25V to +3.8V Differential HSTL/LVPECL
Operation-2.25V to -3.8V LVECL Operation30ps (typ) Part-to-Part Skew12ps (typ) Output-to-Output Skew312ps (typ) Propagation Delay≥
300mV Differential Output at 3GHzOn-Chip Reference for Single-Ended InputsOutput Low with Open InputPin Compatible with MC100LVEP111 (MAX9311)
and MC100EP111 (MAX9313)Offered in Tiny QFN* Package (70% Smaller
Footprint than LQFP)
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data DriversTOP VIEW28293031252627
VCCQ1Q0VCCQ21315141611129Q3
VEE
VBB
CLK0
CLKSEL2VCC
MAX9311
MAX9313Q1Q2
VCCQ8Q9VCCQ7Q9Q8Q7
CLK1
CLK1
CLK0
LQFP (7mm × 7mm), TQFP (5mm × 5mm),
QFN (NO LEADS EXTENDING FROM QFN PACKAGE)
CLKSEL
MAX9311/MAX9313OFF
OFF
CLK0, CLK0CLK1, CLK1
Pin Configuration
Ordering Information19-2078; Rev 2; 10/02
PARTTEMP. RANGEPIN-PACKAGE
MAX9311ECJ-40°C to +85°C32 LQFP (7mm ✕ 7mm)
MAX9311EGJ*-40°C to +85°C32 QFN (5mm ✕ 5mm)
MAX9311EHJ*-40°C to +85°C32 TQFP (5mm ✕ 5mm)
MAX9313ECJ-40°C to +85°C32 LQFP (7mm ✕ 7mm)
MAX9313EGJ*-40°C to +85°C32 QFN (5mm ✕ 5mm)
MAX9313EHJ*-40°C to +85°C32 TQFP (5mm ✕ 5mm)
*Future product—contact factory for availability.
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω±1% to VCC- 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC- VEE...............................................................................4.1V
Inputs (CLK_, CLK_, CLKSEL)..............VEE- 0.3V to VCC+ 0.3V
CLK_ to CLK_....................................................................±3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
VBBSink/Source Current...............................................±0.65mA
Junction-to-Ambient Thermal Resistance in Still Air
7mm x 7mm LQFP.....................................................+90°C/W
Junction-to-Ambient Thermal Resistance with
500 LFPM Airflow
7mm x 7mm LQFP.....................................................+60°C/W
Junction-to-Case Thermal Resistance
7mm x 7mm LQFP.....................................................+12°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Human Body Model (CLKSEL, CLK_, CLK_,
Q_, Q_,VBB).......................................................................2kV
Soldering Temperature (10s)...........................................+300°C
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINMAXMINMAXMINMAXUNITS
SINGLE-ENDED INPUT (CLKSEL)AX 9311VCC
- 1.23VCCVCC
- 1.23VCCVCC
- 1.23VCC
Input High
VoltageVIH
Inter nal B B
thr eshol d M AX 9313VCC
- 1.165VCCVCC
- 1.165VCCVCC
- 1.165VCCAX 9311VEEVCC
- 1.62VEEVCC
- 1.62VEEVCC
- 1.62Input Low
VoltageVIL
Inter nal B B
thr eshol d M AX 9313VEEVCC
- 1.475VEEVCC
- 1.475VEEVCC
- 1.475
Input High
CurrentIIH150150150µA
Input Low
CurrentIIL-10+10-10+10-10+10µA
DIFFERENTIAL INPUTS (CLK_, CLK_)AX 9311VCC
- 1.23VCCVCC
- 1.23VCCVCC
- 1.23VCCSingle-Ended
Input High
VoltageVIHBB
connected
to CLK_V IL for V BB
connected
to C LK_) ,
Figure 1AX 9313VCC
- 1.165VCCVCC
- 1.165VCCVCC
- 1.165VCC
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)(VCC- VEE= +2.25V to +3.8V, outputs loaded with 50Ω±1% to VCC- 2V, CLKSEL = high or low, unless otherwise noted.) (Notes 1–4)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINMAXMINMAXMINMAXUNITSAX 9311VEEVCC
- 1.62VEEVCC
- 1.62VEEVCC
-1.62Single-Ended
Input Low
VoltageVILBB
connected
to CLK_V IH for V BB
connected
to C LK_) ,
Figure 1AX 9313VEEVCC
- 1.475VEEVCC
- 1.475VEEVCC
High Voltage
of Differential
Input
VIHDVEE +1.2VCCVEE + 1.2VCCVEE +1.2VCCV
Low Voltage
of Differential
Input
VILDVEEVCC
- 0.095VEEVCC
- 0.095VEEVCC
- 0.095V
For VCC - VEE < 3.0V0.095VCC
- VEE0.095VCC
- VEE0.095VCC
- VEEDifferential
Input Voltage
VIHD -
VILDFor VCC - VEE ≥ 3.0V0.0953.00.0953.00.0953.0
Input High
CurrentIIH150150150µA
CLK_ Input Low
CurrentIILCLK-10+10-10+10-10+10µA
CLK_ Input Low
CurrentIILCLK-150-150-150µA
OUTPUTS (Q_, Q_)Single-Ended
Output High
Voltage
VOHFigure 1VCC
- 1.025
VCC
- 0.900
VCC
- 1.025
VCC
- 0.900
VCC
- 1.025
VCC
- 0.900V
Single-Ended
Output Low
Voltage
VOLFigure 1VCC
- 1.93
VCC
- 1.695
VCC
- 1.93
VCC
- 1.695
VCC
- 1.93
VCC
- 1.695V
Differential
Output Voltage
VOH -
VOLFigure 1670950670950670950mV
REFERENCE (VBB)AX 9311V C C 1.525C C 1.325C C 1.525C C 1.325C C 1.525C C 1.325Reference
Voltage Output
(Note 5)
VBBIBB =
±0.5mAM AX 9313VCC
- 1.38
VCC
- 1.26
VCC
- 1.38
VCC
- 1.26
VCC
- 1.38
VCC
- 1.26
POWER SUPPLYSupply Current
(Note 6)IEE758295mA
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
AC ELECTRICAL CHARACTERISTICS(VCC- VEE= 2.25V to 3.8V, outputs loaded with 50Ω±1% to VCC- 2V, input frequency = 1.5GHz, input transition time = 125ps
(20% to 80%), CLKSEL = high or low, VIHD= VEE+ 1.2V to VCC, VILD= VEEto VCC- 0.15V, VIHD- VILD= 0.15V to the smaller of 3V or
VCC- VEE, unless otherwise noted. Typical values are at VCC- VEE= 3.3V, VIHD= VCC-1V, VILD= VCC-1.5V.) (Note 7)
-40°C+25°C+85°CPARAMETERSYMBOLCONDITIONSMINTYPMAXMINTYPMAMINTYPMAXUNITSDifferential
Input-to-
Output Delay
tPLHD,
tPHLDFigure 2220321380220312410260322400ps
Output-to-
Output Skew
(Note 8)
tSKOO124612461035ps
Part-to-Part
Skew (Note 9)tSKPP301603019030140ps
fIN = 1.5GH z,l ock p atter n1.22.51.22.51.22.5Added
Random Jitter
(Note 10)
tRJ
fIN = 3.0GH z,l ock p atter n1.22.61.22.61.22.6
(RMS)
Added
Deterministic
Jitter (Note 10)
tDJ
3Gbps,
223 -1 PRBS
pattern9580958095ps
(p-p)
VOH - VOL ≥
350mV, Clock
pattern,
Figure 2
Switching
FrequencyfMAX
VOH - VOL ≥
500mV, Clock
pattern,
Figure 2
GHz
Output
Rise/Fall Time
(20% to 80%)
tR, tFFigure 2100112140100116140100121140ps
Note 1:Measurements are made with the device in thermal equilibrium.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:Single-ended input operation using VBBis limited to VCC- VEE= 3.0V to 3.8V for the MAX9311 and VCC- VEE= 2.7V to 3.8V
for the MAX9313.
Note 4:DCparameters production tested at TA= +25°C. Guaranteed by design and characterization over the full operating temper-
ature range.
Note 5:Use VBBonly for inputs that are on the same device as the VBBreference.
Note 6:All pins open except VCCand VEE.
Note 7:Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9:Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge
transition.
Note 10:Device jitter added to the input signal.
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Typical Operating Characteristics(VCC= +3.3V, VEE= 0, VIHD= VCC- 0.95V, VILD= VCC- 1.25V, input transition time = 125ps (20% to 80%), fIN= 1.5GHz, outputs
loaded with 50Ωto VCC- 2V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT (IEE)
vs. TEMPERATURE
MAX9311 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
OUTPUT AMPLITUDE (VOH - VOL)
vs. FREQUENCY
MAX9311 toc02
FREQUENCY (MHz)
OUTPUT AMPLITUDE (V)
TRANSITION TIME vs. TEMPERATURE
MAX9311 toc03
TEMPERATURE (°C)
TRANSITION TIME (ps)
125tR
PROPAGATION DELAY
vs. HIGH VOLTAGE OF
DIFFERENTIAL INPUT (VIHD)
MAX9311 toc04
VIHD (V)
PROPAGATION DELAY (ps)
tPLHD
tPHLD
VIHD - VILD = 150mV
PROPAGATION DELAY
vs. TEMPERATURE
MAX9311 toc05
TEMPERATURE (°C)
PROPAGATION DELAY (ps)VIHD = VCC - 0.95V
VILD = VCC - 1.1V
tPLHD
tPHLD
MAX9311/MAX9313
1:10 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
Pin Description
PINNAMEFUNCTION1, 9, 16,
25, 32VCCPositive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.CLKSEL
Clock Select Input (Single-Ended). Drive low to select the CLK0, CLK0 input. Drive high to select the
CLK1, CLK1 input. The CLKSEL threshold is VBB. If CLKSEL is not driven by a logic signal, use a 1kΩ
pulldown to VEE to select CLK0, CLK0, or a 1kΩ pullup to VCC to select CLK1, CLK1.CLK0Noninverting Differential Clock Input 0. Internal 75kΩ pulldown resistor.CLK0Inverting Differential Clock Input 0. Internal 75kΩ pullup and pulldown resistors.
5VBBRefer ence Outp ut V ol tag e. C onnect to the i nver ti ng or noni nver ti ng cl ock i np ut to p r ovi d e a r efer ence for
si ng l e- end ed op er ati on. W hen used , b yp ass w i th a 0.01µF cer am i c cap aci tor to V C C ; other w i se, l eave op en.CLK1Noninverting Differential Clock Input 1. Internal 75kΩ pulldown resistor.CLK1Inverting Differential Clock Input 1. Internal 75kΩ pullup and pulldown resistors.
8VEENegative Supply VoltageQ9Inverting Q9 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q9Noninverting Q9 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q8Inverting Q8 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q8Noninverting Q8 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q7Inverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q7Noninverting Q7 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q6Inverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q6Noninverting Q6 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q5Inverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q5Noninverting Q5 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q4Inverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q4Noninverting Q4 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q3Inverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q3Noninverting Q3 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q2Inverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q2Noninverting Q2 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q1Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q1Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q0Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.Q0Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
