MAX9260GCB/V+T ,Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control ChannelApplications Circuit appears at end of data sheet.For pricing, delivery, and ordering information, ..
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MAX9260GCB/V+T
Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
EVALUATION KIT AVAILABLE General Description
The MAX9259 serializer pairs with the MAX9260 deseri-
alizer for joint transmission of high-speed video, audio,
and control data.
The MAX9259/MAX9260 operate up to 3.125Gbps for a
15m shielded twisted-pair (STP) cable. This serial link
supports display panels from QVGA (320 x 240) up to
XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480).
The embedded audio channel supports I2S up to 32 bits
per sample and at a 192kHz sample rate. The embed-
ded control channel forms a full-duplex, differential
100kbps to 1Mbps UART link between the serializer and
deserializer. The host electronic control unit (ECU) or
microcontroller (FC) resides either on the MAX9259 or on
the MAX9260. In addition, the control channel enables
ECU/FC control of peripherals in the remote side of the
serial link through I2C/UART.
Preemphasis and channel equalization extend the link
length and enhance the link reliability. Spread spectrum
is available to reduce EMI on the serial and parallel out-
put data signals. The differential link complies with the
ISO 10605 and IEC 61000-4-2 ESD-protection standards.
The core supplies for the MAX9259/MAX9260 are 1.8V
and 3.3V, respectively. Both devices use an I/O sup-
ply from 1.8V to 3.3V. These devices are available in
a 64-pin TQFP package (10mm x 10mm) and a 56-pin
TQFN/QFND package (8mm x 8mm x 0.75mm) with an
exposed pad. Electrical performance is guaranteed over
the -40NC to +105NC automotive temperature range.
Applications
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems
FeaturesIdeal for Digital Video Applications Up to XGA (1280 x 768) or Dual-View WVGA
(2 x 854 x 480) Panels with 18- or 24-Bit Color Pre/Deemphasis Allows 15m Cable at Full Speed Up to 192kHz, 32-Bit Sample I2SMultiple Data Rates for System Flexibility Up to 3.12Gbps Serial-Bit Rate 6.25MHz to 104MHz Pixel Clock Up to 1Mbps UART/UART-to-I2C Control ChannelReduces EMI and Shielding Requirements Serial Output Programmable for 100mV to 400mV Programmable Spread Spectrum Reduces EMI Bypasses Input PLL for Jitter AttenuationPeripheral Features for System Verification
Built-In Serial Link PRBS BER Tester Interrupt Transmission from Deserializer to
Serializer Meets AEC-Q100 Requirements -40NC to +105NC Operating Temperature Range ±10kV Contact and 25kV Air ISO 10605 and
±10kV IEC 61000-4-2 ESD Protection Ordering Information
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel. Simplified DiagramMAX9259MAX9260
VIDEO/AUDIO2C
720p
DISPLAY
VIDEO/AUDIO2C
PARTTEMP RANGEPIN-PACKAGE
MAX9259GCB/V+-40NC to +105NC64 TQFP-EP*
MAX9259GCB/V+T-40NC to +105NC64 TQFP-EP*
MAX9259GTN/V+T-40NC to +105NC56 TQFN-EP*
MAX9259GGN/VY+-40NC to +105NC56 QFND-EP*
MAX9260GCB/V+-40NC to +105NC64 TQFP-EP*
MAX9260GCB/V+T-40NC to +105NC64 TQFP-EP*
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND
MAX9259 ...........................................................-0.5V to +1.9V
MAX9260 ...........................................................-0.5V to +3.9V
DVDD to GND (MAX9259) ...................................-0.5V to +1.9V
DVDD to DGND (MAX9260) .................................-0.5V to +3.9V
IOVDD to GND (MAX9259) ..................................-0.5V to +3.9V
IOVDD to IOGND (MAX9260) ..............................-0.5V to +3.9V
Any Ground to Any Ground .................................-0.5V to +0.5V
OUT+, OUT- to AGND (MAX9259) ......................-0.5V to +1.9V
IN+, IN- to AGND (MAX9260) ..............................-0.5V to +1.9V
LMN_ to GND (MAX9259)
(60kI source impedance) ................................-0.5V to +3.9V
All Other Pins to GND (MAX9259) .......-0.5V to (IOVDD + 0.5V)
All Other Pins to IOGND (MAX9260) ...-0.5V to (IOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or
Supply (MAX9259) .................................................Continuous
IN+, IN- Short Circuit to Ground or
Supply (MAX9260) .................................................Continuous
Continuous Power Dissipation (TA = +70NC)
64-Pin TQFP (derate 31.3mW/NC above +70NC) .......2508mW
56-Pin TQFN (derate 47.6mW/NC above +70NC) ....3809.5mW
56-Pin QFND (derate 42.7mW/NC above +70NC) ......3148mW
Operating Temperature Range ........................-40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................-65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
MAX9259 DC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
ABSOLUTE MAXIMUM RATINGS
64 TQFPJunction-to-Ambient Thermal Resistance (BJA) .......31.9NC/WJunction-to-Case Thermal Resistance (BJC) .................1NC/W
56 TQFNJunction-to-Ambient Thermal Resistance (BJA) ..........21NC/WJunction-to-Case Thermal Resistance (BJC) .................1NC/W
56 QFNDJunction-to-Ambient Thermal Resistance (BJA) .......23.4NC/WJunction-to-Case Thermal Resistance (BJC) ..............1.6NC/W
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-
er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (DIN_, PCLKIN, PWDN, SSEN, BWS, ES, DRS, MS, CDS, AUTOS, SD, SCK, WS)
High-Level Input VoltageVIH10.65 x
VIOVDDV
Low-Level Input VoltageVIL10.35 x
VIOVDDV
Input CurrentIIN1VIN = 0 to VIOVDD-10+10FA
Input Clamp VoltageVCLICL = -18mA-1.5V
SINGLE-ENDED OUTPUT (INT)
High-Level Output VoltageVOH1IOH = -2mAVIOVDD
- 0.2V
Low-Level Output VoltageVOL1IOL = 2mA0.2V
Output Short-Circuit CurrentIOSVO = 0VVIOVDD = 3.0V to 3.6V163564mAVIOVDD = 1.7V to 1.9V31221
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9259 DC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)
High-Level Input VoltageVIH20.7 x
VIOVDDV
Low-Level Input VoltageVIL20.3 x
VIOVDDV
Input CurrentIIN2VIN = 0 to VIOVDD (Note 2)-110+5FA
Low-Level Open-Drain Output
VoltageVOL2IOL = 3mAVIOVDD = 1.7V to 1.9V0.4VVIOVDD = 3.0V to 3.6V0.3
DIFFERENTIAL OUTPUT (OUT+, OUT-)
Differential Output VoltageVOD
Preemphasis off (Figure 1)300400500
mVP-P
3.3dB preemphasis setting, VOD(P)
(Figure 2)350610
3.3dB deemphasis setting, VOD(D)
(Figure 2)240425
Change in VOD Between
Complementary Output StatesDVOD15mV
Output Offset Voltage,
(VOUT+ + VOUT-)/2 = VOSVOSPreemphasis off1.11.41.56V
Change in VOS Between
Complementary Output StatesDVOS15mV
Output Short-Circuit CurrentIOSVOUT+ or VOUT- = 0V-60mAVOUT+ or VOUT- = 1.9V25
Magnitude of Differential Output
Short-Circuit CurrentIOSDVOD = 0V25mA
Output Termination Resistance
(Internal)ROFrom OUT+, OUT- to VAVDD455463I
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching ThresholdVCHR27mV
Low Switching ThresholdVCLR-27mV
LINE-FAULT-DETECTION INPUT (LMN_)
Short-to-GND ThresholdVTGFigure 30.3V
Normal ThresholdsVTNFigure 30.571.07V
Open ThresholdsVTOFigure 31.45VIO+
0.06V
Open Input VoltageVIOFigure 31.471.75V
Short-to-Battery ThresholdVTEFigure 32.47V
POWER SUPPLY
Worst-Case Supply Current
(Figure 4)IWCSBWS = GND
fPCLKIN = 16.6MHz100125fPCLKIN = 33.3MHz105145
fPCLKIN = 66.6MHz116155
fPCLKIN = 104MHz135175
Sleep-Mode Supply CurrentICCS40110FA
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9259 DC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
ESD PROTECTION
OUT+, OUT- (Pin to EP)VESD
Human Body Model, RD = 1.5kW,
CS = 100pF±8IEC 61000-4-2,
RD = 330W,
CS = 150pF
Contact discharge±10
Air discharge±12
IEC 10605,
RD = 2kW,
CS = 330pF
Contact discharge±10
Air discharge±25
All Other Pins (to EP or Supply)VESDHuman Body Model, RD = 1.5kW,
CS = 100pF±4FA
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9259 AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PARALLEL CLOCK INPUT (PCLKIN)
Clock FrequencyfPCLKIN
VBWS = VGND, VDRS = VIOVDD8.3316.66
MHzVBWS = VGND, VDRS = VGND16.66104
VBWS = VIOVDD, VDRS = VIOVDD6.2512.5
VBWS = VIOVDD, VDRS = VGND12.578
Clock Duty CycleDCtHIGH/tT or tLOW/tT (Figure 5)355065%
Clock Transition TimetR, tF(Figure 5)4ns
Clock JittertJ3.125Gbps, 300kHz sinusoidal jitter800ps(P-P)
I2C/UART PORT TIMING (Note 3)
Output Rise TimetR30% to 70%, CL = 10pF to 100pF, 1kI
pullup to IOVDD20150ns
Output Fall TimetF70% to 30%, CL = 10pF to 100pF, 1kI
pullup to IOVDD20150ns
Input Setup TimetSETI2C only (Figure 6)100ns
Input Hold TimetHOLDI2C only (Figure 6)0ns
SWITCHING CHARACTERISTICS (Note 3)
Differential Output Rise-and-Fall
TimetR, tF20% to 80%, VOD ≥ 400mV, RL = 100I,
serial-data rate = 3.125Gbps90150ps
Total Serial Output JittertTSOJ1
3.125Gbps PRBS signal, measured at
VOD = 0V differential, preemphasis
disabled (Figure 7)
0.25UI
Deterministic Serial Output JittertDSOJ23.125Gbps PRBS signal0.15UI
Parallel Data Input Setup TimetSET(Figure 8)1ns
Parallel Data Input Hold TimetHOLD(Figure 8)1.5ns
Serializer Delay (Note 4)tSD(Figure 9)Spread spectrum enabled2830BitsSpread spectrum disabled270
Link Start TimetLOCK(Figure 10)3.5ms
Power-Up TimetPU(Figure 11)3.5ms
I2S INPUT TIMING
WS FrequencyfWS(Table 2)8192kHz
Sample Word LengthnWS(Table 2)432Bits
SCK FrequencyfSCKfSCK = fWS x nWS x 2(8 x 4)
x 2
(192 x
32) x 2kHz
SCK Clock High Time (Note 3)tHCVSCK ≥ VIH, tSCK = 1/fSCK0.35 x
tSCKns
SCK Clock Low Time (Note 3)tLCVSCK ≤ VIL, tSCK = 1/fSCK0.35 x
tSCKns
SD, WS Setup TimetSET(Figure 12, Note 3)2ns
SD, WS Hold TimetHOLD(Figure 12, Note 3)2ns
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9260 DC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS)
High-Level Input VoltageVIH10.65 x
VIOVDDV
Low-Level Input VoltageVIL10.35 x
VIOVDDV
Input CurrentIIN1VIN = 0 to VIOVDD-10+10FA
Input Clamp VoltageVCLICL = -18mA-1.5V
SINGLE-ENDED OUTPUTS (DOUT_, SD, WS, SCK, PCLKOUT)
High-Level Output VoltageVOHIOH = -2mA
VDCS = VIOGNDVIOVDD
- 0.3V
VDCS = VIOVDDVIOVDD
- 0.2
Low-Level Output VoltageVOL1IOL = 2mAVDCS = VIOGND0.3VVDCS = VIOVDD0.2
Output Short-Circuit CurrentIOS
DOUT_,
SD, WS,
SCK
VO = 0V,
VDCS = VIOGND
VIOVDD =
3.0V to 3.6V152539
VIOVDD =
1.7V to 1.9V3713
VO = 0V,
VDCS = VIOVDD
VIOVDD =
3.0V to 3.6V203563
VIOVDD =
1.7V to 1.9V51021
PCLKOUT
VO = 0V,
VDCS = VIOGND
VIOVDD =
3.0V to 3.6V153350
VIOVDD =
1.7V to 1.9V51017
VO = 0V,
VDCS = VIOVDD
VIOVDD =
3.0V to 3.6V305497
VIOVDD =
1.7V to 1.9V91632
I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, ERR, GPIO_, LOCK)
High-Level Input VoltageVIH20.7 x
VIOVDDV
Low-Level Input VoltageVIL20.3 x
VIOVDDV
Input CurrentIIN2VIN = 0 to VIOVDD
(Note 2)
RX/SDA, TX/SCL-110+1FAGPIO, ERR, LOCK-80+1
Low-Level Open-Drain Output
VoltageVOL2IOL = 3mAVIOVDD = 1.7V to 1.9V0.4V
VIOVDD = 3.0V to 3.6V0.3V
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9260 DC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage, (VIN+) - (VIN-)VROHNo high-speed data transmission
(Figure 13)3060mV
Differential Low Output Peak
Voltage, (VIN+) - (VIN-)VROLNo high-speed data transmission
(Figure 13)-60-30mV
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
(Peak), (VIN+) - (VIN-)VIDH(P)(Figure 14)4090mV
Differential Low Input Threshold
(Peak), (VIN+) - (VIN-)VIDL(P)(Figure 14)-90-40mV
Input Common-Mode Voltage,
((VIN+) + (VIN-))/2VCMR11.31.6V
Differential Input Resistance
(Internal)RI80100130I
POWER SUPPLY
Worst-Case Supply Current
(Figure 15)IWCS
VBWS = VIOGND,
fPCLKOUT = 16.6MHz
2% spread
spectrum active113166
Spread spectrum
disabled105155
VBWS = VIOGND,
fPCLKOUT = 33.3MHz
2% spread
spectrum active122181
Spread spectrum
disabled110165
VBWS = VIOGND,
fPCLKOUT = 66.6MHz
2% spread
spectrum active137211
Spread spectrum
disabled120188
VBWS = VIOGND,
fPCLKOUT = 104MHz
2% spread
spectrum active159247
Spread spectrum
disabled135214
Sleep-Mode Supply CurrentICCS80130FA
Power-Down Supply CurrentICCZVPWDN = VIOGND1970FA
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
ESD PROTECTION
IN+, IN- (Pin to EP)VESD
Human Body Model, RD = 1.5kW,
CS = 100pF±8
IEC 61000-4-2,
RD = 330W,
CS = 150pF
Contact discharge±8
Air discharge±10
IEC 10605,
RD = 2kW,
CS = 330pF
Contact discharge±8
Air discharge±20
All Other Pins (to EP or Supply)VESDHuman Body Model, RD = 1.5kW,
CS = 100pF±4FA
MAX9260 DC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.)
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9260 AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock FrequencyfPCLKOUT
VBWS = VIOGND, VDRS = VIOVDD8.3316.66
MHzVBWS = VIOGND, VDRS = VIOGND16.66104
VBWS = VIOVDD, VDRS = VIOVDD6.2512.5
VBWS = VIOVDD, VDRS = VIOGND12.578
Clock Duty CycleDCtHIGH/tT or tLOW/tT (Figure 16)405060%
Clock JittertJPeriod jitter, RMS, spread off, 3.125Gbps,
PRBS pattern, UI = 1/fPCLKOUT0.05UI
I2C/UART PORT TIMING
Output Rise TimetR30% to 70%, CL = 10pF to 100pF, 1kI
pullup to IOVDD20150ns
Output Fall TimetF70% to 30%, CL = 10pF to 100pF, 1kI
pullup to IOVDD20150ns
Input Setup TimetSETI2C only100ns
Input Hold TimetHOLDI2C only0ns
SWITCHING CHARACTERISTICS
PCLKOUT Rise-and-Fall TimetR, tF
20% to 80%,
VIOVDD = 1.7V to 1.9V
VDCS = VIOVDD,
CL = 10pF0.42.2
VDCS = VIOGND,
CL = 5pF0.52.8
20% to 80%,
VIOVDD = 3.0V to 3.6V
VDCS = VIOVDD,
CL = 10pF0.251.7
VDCS = VIOGND,
CL = 5pF0.32.0
Parallel Data Rise-and-Fall Time
(Figure 17)tR, tF
20% to 80%,
VIOVDD = 1.7V to 1.9V
VDCS = VIOVDD,
CL = 10pF0.53.1
VDCS = VIOGND,
CL = 5pF0.63.8
20% to 80%,
VIOVDD = 3.0V to 3.6V
VDCS = VIOVDD,
CL = 10pF0.32.2
VDCS = VIOGND,
CL = 5pF0.42.4
Deserializer DelaytSDSpread spectrum enabled (Figure 18)2880BitsSpread spectrum disabled (Figure 18)750
Lock TimetLOCKSpread spectrum enabled (Figure 19)1500FsSpread spectrum off (Figure 19)1000
Power-Up TimetPU(Figure 20)2500Fs
Reverse Control-Channel Output
Rise TimetRNo high-speed transmission (Figure 13)180400ns
Reverse Control-Channel Output
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Typical Operating Characteristics
(VDVDD = VAVDD = VIOVDD = 1.8V (MAX9259), VDVDD = VAVDD = VIOVDD = 3.3V (MAX9260), TA = +25NC, unless otherwise noted.)
MAX9260 AC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.)
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Not production tested.
Note 4: Bit time = 1/(30 x fRXCLKIN) (BWS = 0), = 1/(40 x fRXCLKIN) (BWS = VIOVDD).
Note 5: Rising to rising edge jitter can be twice as large.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I2S OUTPUT TIMING
WS JittertAJ-WS
tWS = 1/fWS, rising
(falling) edge to
falling (rising) edge
(Note 5)
fWS = 48kHz or
44.1kHz
0.4e - 3
x tWS
0.5e - 3
x tWSfWS = 96kHz0.8e - 3
x tWS
1e - 3
x tWS
fWS = 192kHz1.6e - 3
x tWS
2e - 3
x tWS
SCK JittertAJ-SCK
tSCK = 1/fSCK, ris-
ing edge to rising
edge
nWS = 16 bits,
fWS = 48kHz or 44.1kHz
13e - 3
x tSCK
16e - 3
x tSCKnWS = 24 bits,
fWS = 96kHz
39e - 3
x tSCK
48e - 3
x tSCK
nWS = 32 bits,
fWS = 192kHz
0.1
x tSCK
0.13
x tSCK
Audio Skew Relative to VideoASKVideo and audio synchronized3 x tWS4 x tWSµs
SCK, SD, WS Rise-and-Fall TimetR, tF20% to 80%VDCS = VIOVDD, CL = 10pF0.33.1ns
VDCS = VIOGND, CL = 5pF0.43.8ns
SD, WS Valid Time Before SCKtDVBtSCK = 1/fSCK (Figure 21)0.35
x tSCK
0.5
x tSCKns
SD, WS Valid Time After SCKtDVAtSCK = 1/fSCK (Figure 21)0.35
x tSCK
0.5
x tSCKns
MAX9259 SUPPLY CURRENT
vs. PCLKIN FREQUENCY (24-BIT MODE)
MAX9259/60 toc01
SUPPLY CURRENT (mA)654525
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS = 0x00
MAX9259 SUPPLY CURRENT
vs. PCLKIN FREQUENCY (32-BIT MODE)
MAX9259/60 toc02
SUPPLY CURRENT (mA)503520
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS = 0x00
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (24-BIT MODE)
SUPPLY CURRENT (mA)654525
MAX9259/60 toc03
ALL EQUALIZER SETTINGS
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Typical Operating Characteristics (continued)
(VDVDD = VAVDD = VIOVDD = 1.8V (MAX9259), VDVDD = VAVDD = VIOVDD = 3.3V (MAX9260), TA = +25NC, unless otherwise noted.)
MAXIMUM PCLKIN FREQUENCY vs.
STP CABLE LENGTH (BER < 10-9)
FREQUENCY (MHz)105
MAX9259/60 toc12OPTIMUM PE/EQ
SETTINGS
BER CAN BE < 10-12 FOR
CABLE LENGTHS LESS THAN 10m
NO PE, EQS = LOW
NO PE, EQS = HIGH
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY
(MAX9260 SPREAD ON, MAX9259 SPREAD OFF)
PCLKOUT OUTPUT POWER (dBm)43404142
MAX9259/60 toc110% SPREAD
4% SPREAD2% SPREAD
fPCLKOUT = 42MHz
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY
(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)
PCLKOUT OUTPUT POWER (dBm)43404142
MAX9259/60 toc100% SPREAD0.5% SPREAD
4% SPREAD2% SPREAD
fPCLKOUT = 42MHz
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY
(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)
PCLKOUT FREQUENCY (MHz)
PCLKOUT OUTPUT POWER (dBm)
MAX9259/60 toc090% SPREAD0.5% SPREAD
4% SPREAD2% SPREAD
fPCLKOUT = 20MHz
SERIAL LINK SWITCHING PATTERN
WITH 14dB PREEMPHASIS
(PARALLEL BIT RATE = 104MHz, 10m STP CABLE)
MAX9259/60 toc08
250.0mV
-250.0mV52.00ps/div
3.12Gbps
SERIAL LINK SWITCHING PATTERN
WITHOUT PREEMPHASIS
(PARALLEL BIT RATE = 104MHz, 10m STP CABLE)
MAX9259/60 toc07
400.0mV3.12Gbps
-400.0mV52.00ps/div
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (32-BIT MODE)
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)502035
MAX9259/60 toc062%, 4% SPREAD
NO SPREAD
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (24-BIT MODE)
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)652545
MAX9259/60 toc052%, 4% SPREAD
NO SPREAD
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (32-BIT MODE)
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT (mA)503520
MAX9259/60 toc04
ALL EQUALIZER SETTINGS
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Pin Configurations394041424344454647
DIN8
DIN14
TOP VIEW
DRSINTLMN0AVDDOUT+OUT-AGNDLMN1
SSENTX/SCLRX/SDAPWDNCDS
DIN13DIN16DIN15
IOVDD
PCLKIN
AGND
GND
DIN17
AVDD
DIN19DIN18DIN21DIN20DIN22
GND
IOVDD
AUTOS
SCK
DIN28
DIN27
DIN26
DIN2534353637
DIN24
GND
DVDD
AGND
DIN23
DIN7
DIN6
DIN5
DIN4
DIN3
DIN11
DIN10
DVDD
GND
DIN9
DIN2
DIN1
IOVDD
GNDDIN0
BWS
DIN12109876543216151413121
MAX9259
MAX9259
LFLT
EP*
TQFP
(10mm × 10mm × 1mm)394041424344454647
DOUT0
INT
DOUT10
TQFP
(10mm × 10mm × 1mm)TOP VIEW
DOUT11DOUT12DOUT14DOUT15PCLKOUTDOUT16DOUT17DOUT18
DOUT19DOUT20DOUT21DOUT22DOUT23
BWS
GPIO0
CDS
AVDD
IN-
IN+
EQS
AGND
DCS
GPIO1
DVDD
DGND
IOGND
IOVDD
DOUT25
DOUT26
DOUT27
DOUT28/MCLK
SCK
LOCK34353637
IOGND
ERR
PWDN
TX/SCL
RX/SDA
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
AGND
AVDD
DRS
SSEN
IOGND
DOUT6
DOUT7
IOVDD
IOGND
DOUT24DOUT8
DOUT9
ENABLE
MAX9260
DOUT13
EP*
EP*109876543216151413121
TOP VIEW
TQFN/QFND
(8mm x 8mm x 0.75mm)DIN23
DVDD
DIN24
DIN25
DIN26
DIN27
DIN28
SCK
AUTOS
IOVDD
CDS
DIN11
DIN10
DVDD
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
IOVDD
DIN0
*CONNECT EP TO GROUND PLANE56789101112131441403938373635343332313029
DIN20DIN21DIN22DIN19DIN18DIN17
AVDD
IOVDD
PCLKIN
DIN16DIN15DIN14DIN13DIN12
TX/SCLRX/SDAPWDNSSENLMN1OUT-OUT+AVDDLMN0LFLTINTDRSESBWS
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9259 Pin Description
PINNAMEFUNCTIONTQFPTQFN/QFND
1–5, 11–17,
21–25, 49,
52–60, 63,
1–5, 9–15,
17–21, 43,
45–53, 55,
DIN0–
DIN28
Data Input[0:28]. Parallel data inputs. All pins internally pulled down to GND. Selected
edge of PCLKIN latches input data. Set BWS = low (24-bit mode) to use DIN0–DIN20
(RGB and SYNC). DIN21–DIN28 are not used in 24-bit mode. Set BWS = high (32-bit
mode) to use DIN0–DIN28 (RGB, SYNC, and two extra inputs).6PCLKINParallel Clock Input. Latches parallel data inputs and provides the PLL reference clock.
7, 30, 517, 26, 44IOVDD
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with
0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value
capacitor closest to IOVDD.
8, 20, 31,
50, 61—GNDDigital and I/O Ground
9, 18, 39—AGNDAnalog Ground
10, 428, 36AVDD1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors
as close as possible to the device with the smaller value capacitor closest to AVDD.
19, 6216, 54DVDD1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to DVDD.22SDI2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD as an
additional data input latched on the selected edge of PCLKIN.23SCKI2S Serial-Clock Input with Internal Pulldown to GND24WSI2S Word-Select Input with Internal Pulldown to GND25AUTOS
Autostart Setting. Active-low power-up mode selection input requires external pulldown
or pullup resistors. Set AUTOS = high to power up the device with no link active. Set
AUTOS = low to have the MAX9259 power up the serial link with autorange detection
(see Tables 11 and 12).27MSMode Select. Control-link mode-selection input requires external pulldown or pullup
resistors. Set MS = low, to select base mode. Set MS = high to select the bypass mode.28CDS
Control-Direction Selection. Control-link-direction selection input requires external
pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the
serial link. Set CDS = high for FC use on the MAX9260 side of the serial link.29PWDNPower-Down. Active-low power-down input requires external pulldown or pullup
resistors.30RX/SDA
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI
pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9259’s UART. In I2C
mode, RX/SDA is the SDA input/output of the MAX9259’s I2C master.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9259 Pin Description (continued)
PINNAMEFUNCTIONTQFPTQFN/QFND31TX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In
I2C mode, TX/SCL is the SCL output of the MAX9259’s I2C master.32SSEN
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistors. The state of SSEN latches upon power-up or when
resuming from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread
spectrum on the serial link. Set SSEN = low to use the serial link without spread spectrum.33LMN1Line-Fault Monitor Input 1 (see Figure 3 for details)
40, 4134, 35OUT-,
OUT+Differential CML Output -/+. Differential outputs of the serial link. 37LMN0Line-Fault Monitor Input 0 (see Figure 3 for details)38LFLTLine Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor.
LFLT = low indicates a line fault. LFLT is output high when PWDN = low.39INT
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT
output.40DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).41ES
Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup
resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger
on the falling edge of PCLKIN.42BWS
Bus-Width Select. Parallel input bus-width selection input requires external pulldown
or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus
mode.—EP
Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND
(TQFN package). MUST externally connect EP to the AGND plane to maximize thermal
and electrical performance.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9260 Pin Description
PINNAMEFUNCTIONENABLE
Enable. Active-low parallel output-enable input requires external pulldown or pullup
resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel
outputs, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to
high impedance.BWS
Bus-Width Select. Parallel output bus-width selection input requires external pulldown
or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus
mode.INTInterrupt. Interrupt input requires external pulldown or pullup resistors. A transition on the
INT input of the MAX9260 toggles the MAX9259’s INT output.CDS
Control-Direction Selection. Control-link-direction selection input requires external
pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the
serial link. Set CDS = high for FC use on the MAX9260 side of the serial link.GPIO0GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.ESEdge Select. PCLKOUT edge-selection input requires external pulldown or pullup
resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
7, 63AVDD3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1µF and 0.001µF capacitors
as close as possible to the device with the smallest value capacitor closest to AVDD.
8 , 9IN+, IN-Differential CML Input +/-. Differential inputs of the serial link.
10, 64AGNDAnalog GroundEQS
Equalizer Select. Deserializer equalizer-selection input requires external pulldown or
pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set
EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB
equalizer boost (EQTUNE = 0100).GPIO1GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.DCS
Drive Current Select. Driver current-selection input requires external pulldown or
pullup resistors. Set DCS = high for stronger parallel data and clock output drivers. Set
DCS = low for normal parallel data and clock drivers (see the MAX9260 DC Electrical
Characteristics table).MS
Mode Select. Control-link mode-selection/autostart mode selection input requires
external pulldown or pullup resistors. MS sets the control-link mode when CDS = high
(see the Control-Channel and Register Programming section). Set MS = low to select
base mode. Set MS = high to select the bypass mode. MS sets autostart mode when
CDS = low (see Tables 11 and 12).DVDD3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors
as close as possible to the device with the smaller value capacitor closest to DVDD.DGNDDigital GroundRX/SDA
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI
pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9260’s UART. In I2C
mode, RX/SDA is the SDA input/output of the MAX9259’s I2C master.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
MAX9260 Pin Description (continued)
PINNAMEFUNCTIONTX/SCL
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I2C
mode, TX/SCL is the SCL output of the MAX9260’s I2C master.PWDNPower-Down. Active-low power-down input requires external pulldown or pullup
resistors.ERR
Error. Active-low open-drain video data error output with internal pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceed a
programmed error threshold or when at least one PRBS error is detected during PRBS
test. ERR is output high when PWDN = low.
21, 31, 50, 60IOGNDInput/Output GroundLOCK
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are
not locked or incorrect serial-word-boundary alignment. LOCK remains low when the
configuration link is active. LOCK is output high when PWDN = low.WSWord Select. I2S word-select output.SCKSerial Clock. I2S serial-clock outputSDSerial Data. I2S serial-data output. Disable I2S to use SD as an additional data output
latched on the selected edge of PCLKOUT.
26–29, 32–40,
42–49, 52–59
DOUT0–
DOUT27,
DOUT28/MCLK
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected
edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and
SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS =
high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs).
DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio
Applications section).
30, 51IOVDD
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smaller value capacitor closest to
IOVDD.PCLKOUTParallel Clock Output. Used for DOUT0–DOUT28.SSEN
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires
external pulldown or pullup resistors. The state of SSEN latches upon power-up or when
resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread
spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs without
spread spectrum.DRS
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).EPExposed Pad. EP internally connected to AGND. MUST externally connect EP to the
AGND plane to maximize thermal and electrical performance.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Functional Diagram
FILTER
PLL
AUDIO
FIFO
PRBS
GEN
SPREAD
PLL
LINE-
FAULT
DET
CMLP S
8B/10B
ENCODE
PARITY
FIFODIN[N:0]
WS, SD, SCK
OUT+
OUT-
LMN0
LMN1
PCLKIN
TX/SCL
RX/SDA
CLKDIV
UART/I2C
TERM
REV CH
LFLT
SPREAD
PLL
AUDIO
FIFO
PRBS
CHECK
CDR
PLL
CMLP S
8B/10B
DECODE
PARITY
FIFODOUT[N:0]
WS, SD, SCK
IN-
STP CABLE
(Z0 = 50)
IN+
PCLKOUT
SERIALIZER
DESERIALIZER
TX/SCL
RX/SDA
CLKDIV
UART/I2C
TERM
REV CH
MAX9259
MAX9260
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 1. MAX9259 Serial Output Parameters
Figure 2. Output Waveforms at OUT+ and OUT-
OUT-
VOD
VOS
GND
RL/2
RL/2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
VOS(-)VOS(+)
((OUT+) + (OUT-))/2
VOS(-)
VOD(-)VOD(-)
VOD = 0V
DVOS = |VOS(+) - VOS(-)|
DVOD = |VOD(+) - VOD(-)|
VOD(+)
OUT+
OUT-
VOSVOD(P)VOD(D)
SERIAL-BIT
TIME
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 3. Fault-Detector Circuit
Figure 4. MAX9259 Worst-Case Pattern Input
OUTPUT
LOGIC
(OUT+)
2.1V
LFLT1.5V
0.5V
REFERENCE
VOLTAGE
GENERATOR
CONNECTORS
*Q1% TOLERANCE
OUTPUT
LOGIC
(OUT-)
MAX9259
45.3kI*
LMN1
LMN0
45.3kI*
1.7V TO 1.9V
4.99kI*
49.9kI*49.9kI*
4.99kI*
TWISTED PAIROUT+
OUT-
PCLKIN
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
DIN_
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 5. MAX9259 Parallel Input Clock Requirements
Figure 6. I2C Timing Parameters
Figure 7. Differential Output Template
VIL MAX
tHIGH
tLOWtF
VIH MIN
PCLKIN
PROTOCOL
SCL
SDA
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
tSU;STA
VIOVDD x 0.7
VIOVDD x 0.7
VIOVDD x 0.3
VIOVDD x 0.3
tLOWtHIGH
tBUF
tHD;STA
tSP
tSU;DATtHD;DATtVD;DATtVD;ACKtSU;STO
1/fSCL
800mV
tTSOJ1
tTSOJ1
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 8. MAX9259 Input Setup-and-Hold Times
Figure 9. MAX9259 Serializer Delay
VIH MIN
VIH MINVIH MIN
VIL MAXVIL MAX
VIL MAX
PCLKIN
DIN_
tHOLDtSET
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
tSDFIRST BITLAST BIT
N+3
EXPANDED TIME SCALE
N+4NN+1N+2
N-1
DIN_
PCLKIN
OUT+/-
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 10. MAX9259 Link Startup Time
Figure 11. MAX9259 Power-Up Delay
SERIAL LINK INACTIVESERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
ENABLED
tLOCK
350Fs
PCLKIN
REVERSE CONTROL CHANNEL
AVAILABLE
PWDN MUST BE HIGH
PWDN
POWERED DOWN
VIH1
tPU
REVERSE CONTROL
CHANNEL DISABLED
350µs
PCLKIN
POWERED UP,
SERIAL LINK INACTIVEPOWERED UP, SERIAL LINK ACTIVE
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
tHOLDtSET
tHOLDtSETtHC
tSCK
tLC
SCK
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 13. MAX9260 Reverse Control-Channel Output Parameters
MAX9260
REVERSE
CONTROL-CHANNEL
TRANSMITTER
IN+
IN-
IN-
IN+
IN+
IN-
VOD
RL/2
RL/2
VCMR
VCMR
VROH
(IN+) - (IN-)
0.1 x VROL
0.9 x VROL
VROL
0.9 x VROH
0.1 x VROH
VIN+
RL/2
RL/2
CINCIN
VID(P)
IN+
IN-
VID(P) = | VIN+ - VIN- |
VCMR = (VIN+ + VIN-)/2
VIN-
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 16. MAX9260 Clock Output High-and-Low Times
Figure 17. MAX9260 Output Rise-and-Fall Times
Figure 18. MAX9260 Deserializer Delay
VOL MAX
tHIGH
tLOW
VOH MIN
PCLKOUT
0.8 x VI0VCC
0.2 x VI0VCCtR
SINGLE-ENDED OUTPUT LOAD
MAX9260
FIRST BIT
IN+/-
DOUT_
PCLKOUT
LAST BIT
SERIAL WORD N
SERIAL-WORD LENGTH
SERIAL WORD N+1SERIAL WORD N+2
tSD
PARALLEL WORD N-2PARALLEL WORD N-1PARALLEL WORD N
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Figure 19. MAX9260 Lock Time
Figure 20. MAX9260 Power-Up Delay
Figure 21. MAX9260 Output I2S Timing Parameters
IN+ - IN-
LOCK
tLOCK
PWDN MUST BE HIGH
VOH
IN+/-
LOCK
tPU
PWDN
VOH
VIH1
tDVA
tDVBtDVAtF
tDVBtR
SCK
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259/MAX9260
Detailed Description
The MAX9259/MAX9260 chipset presents Maxim’s
GMSL technology. The MAX9259 serializer pairs with the
MAX9260 deserializer to form a complete digital serial
link for joint transmission of high-speed video, audio,
and control data for video-display or image-sensing
applications. The serial-payload data rate can reach up
to 2.5Gbps for a 15m STP cable. The parallel interface
is programmable for 24-bit or 32-bit width modes at the
maximum bus clock of 104MHz or 78MHz, respectively.
The minimum bus clock is 6.25MHz for the 32-bit mode
and 8.33MHz for the 24-bit mode. With such a flexible
data configuration, the GMSL is able to support XGA
(1280 x 768) or dual-view WVGA (2 x 854 x 480) display
panels. For image sensing, it supports three 10-bit cam-
era links simultaneously with a pixel clock up to 78MHz.
The 24-bit mode handles 21-bit data and control signals
plus an I2S audio signal. The 32-bit mode handles 29-bit
data and control signals plus an I2S audio signal. Any
combination and sequence of color video data, video
sync, and control signals make up the 21-bit or 29-bit
parallel data on DIN_ and DOUT_. The I2S port supports
the sampled audio data at a rate from 8kHz to 192kHz
and the audio word length of anywhere between 4 to
32 bits. The embedded control channel forms a UART
link between the serializer and deserializer. The UART
link can be set to half-duplex mode or full-duplex mode
depending on the application. The GMSL supports
UART rates from 100kbps to 1Mbps. Using this control
link, a host ECU or FC communicates with the serializer
and deserializer, as well as the peripherals in the remote
side, such as backlight control, grayscale gamma cor-
rection, camera module, and touch screen. All serial
communication (forward and reverse) uses differential
signaling. The peripheral programming uses I2C format
or the default GMSL UART format. A separate bypass
mode enables communication using a full-duplex, user-
defined UART format. The control link between the
MAX9259 and MAX9260 allows FC connectivity to either
device or peripherals to support video-display or image-
sensing applications.
The AC-coupled serial link uses 8B/10B coding. The
MAX9259 serializer features a programmable driver
preemphasis and the MAX9260 deserializer features
a programmable channel equalizer to extend the link
length and enhance the link reliability. Both devices have
a programmable spread-spectrum feature for reducing
EMI on the serial link output (MAX9259) and parallel data
outputs (MAX9260). The differential serial link input and
output pins comply with the ISO 10605 and IEC 61000-
4-2 ESD-protection standards. The core supplies for the
MAX9259/MAX9260 are 1.8V and 3.3V, respectively.
Both devices use an I/O supply from 1.8V to 3.3V
Register Mapping
The FC configures various operating conditions of the
GMSL through registers in the MAX9259/MAX9260.
The default device addresses stored in the R0 and
R1 registers of the MAX9259/MAX9260 are 0x80 and
0x90, respectively. Write to the R0/R1 registers in both
devices to change the device address of the MAX9259
or MAX9260.
