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MAX9248ECM+
27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS DeserializersEVALUATION KIT AVAILABLE
General DescriptionThe MAX9248/MAX9250 digital video serial-to-parallel
converters deserialize a total of 27 bits during data and
control phases. In the data phase, the LVDS serial input is
converted to 18 bits of parallel video data and in the con-
trol phase, the input is converted to 9 bits of parallel con-
trol data. The separate video and control phases take
advantage of video timing to reduce the serial-data rate.
The MAX9248/MAX9250 pair with the MAX9247 serializer
to form a complete digital video transmission system. For
operating frequencies less than 35MHz, the MAX9248/
MAX9250 can also pair with the MAX9217 serializer.
The MAX9248 features spread-spectrum capability,
allowing output data and clock to spread over a speci-
fied frequency range to reduce EMI. The data and
clock outputs are programmable for a spectrum spread
of ±4% or ±2%. The MAX9250 features output enable
input control to allow data busing.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9248/MAX9250 feature a
selectable rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
Contact Discharge and ±30kV Air-Gap Discharge.
The MAX9248/MAX9250 operate from a +3.3V ±10%
core supply and feature a separate output supply for
interfacing to 1.8V to 3.3V logic-level inputs. These
devices are available in a 48-lead LQFP package and
are specified from -40°C to +85°C or -40°C to +105°C.
ApplicationsNavigation System Displays
In-Vehicle Entertainment Systems
Video Cameras
LCD Displays
FeaturesProgrammable ±4% or ±2% Spread-Spectrum
Output for Reduced EMI (MAX9248)Proprietary Data Decoding for DC Balance and
Reduced EMIControl Data Deserialized During Video BlankingFive Control Data Inputs are Single-Bit-Error
TolerantOutput Transition Time is Scaled to Operating
Frequency for Reduced EMIStaggered Output Switching Reduces EMIOutput Enable Allows Busing of Outputs
(MAX9250)Clock Pulse Stretch on LockWide ±2% Reference Clock ToleranceSynchronizes to MAX9247 Serializer Without
External ControlISO 10605 and IEC 61000-4-2 Level 4
ESD ProtectionSeparate Output Supply Allows Interface to 1.8V
to 3.3V Logic+3.3V Core Power SupplySpace-Saving LQFP Package-40°C to +85°C and -40°C to +105°C Operating
Temperature Ranges
PARTTEMP RANGEPIN-PACKAGE
MAX9248ECM+-40°C to +85°C48 LQFP
MAX9248ECM/V+-40°C to +85°C48 LQFP
MAX9248GCM+-40°C to +105°C48 LQFP
MAX9248GCM/V+-40°C to +105°C48 LQFP
MAX9250ECM+-40°C to +85°C48 LQFP
MAX9250ECM/V+-40°C to +85°C48 LQFP
MAX9250GCM+-40°C to +105°C48 LQFP
MAX9250GCM/V+-40°C to +105°C48 LQFP
Ordering Information+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration appears at end of data sheet.
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-mode voltage VCM= VID / 2
to VCC- VID / 2, TA= -40°C to +105°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V, VCM= 1.2V, = +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC_to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
IN+, IN- to LVDSGND............................................-0.5V to +4.0V
IN+, IN- Short Circuit to LVDSGND or VCCLVDS........Continuous
(R/F, OUTEN, RNG_, REFCLK, SS
PWRDWN) to GND.................................-0.5V to (VCC+ 0.5V)
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to VCCOGND.............................-0.5V to (VCCO+ 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C).....1739mW
ESD Protection
Machine Model (RD= 0Ω, CS= 200pF)
All Pins to GND............................................................±200V
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND..............................................................±2kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (IN+, IN-) to GND............................±10kV
Air-Gap Discharge (IN+, IN-) to GND............................±30kV
IEC 61000-4-2 (RD= 330Ω, CS= 150pF)
Contact Discharge (IN+, IN-) to GND............................±10kV
Air-Gap Discharge (IN+, IN-) to GND............................±15kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN, SS)High-Level Input VoltageVIH2.0VCC + 0.3V
Low-Level Input VoltageVIL-0.3+0.8VI N = - 0.3V to 0 ( M AX 9248/AX 9250E C M ) ,I N = - 0.15V to 0 ( M AX 9248/AX 9250G C M ) ,
-100+20Input CurrentIINPWRDWN =
high or low
VIN = 0 to (VCC + 0.3V)-20+20
Input Clamp VoltageVCLICL = -18mA-1.5V
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)IOH = -100µAVCCO - 0.1
IOH = -2mA, RNG1 = highVCCO - 0.35High-Level Output VoltageVOH
IOH = -2mA, RNG1 = lowVCCO - 0.4
IOL = 100µA0.1
IOL = 2mA, RNG1 = high0.3Low-Level Output VoltageVOL
IOL = 2mA, RNG1 = low0.35
High-Impedance Output CurrentIOZPWRDWN = low or OUTEN = low,
VO = -0.3V to (VCCO + 0.3V)-10+10µA
RNG1 = high, VO = 0-10-50Output Short-Circuit CurrentIOSRNG1 = low, VO = 0-7-40mA
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
DC ELECTRICAL CHARACTERISTICS (continued)(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-mode voltage VCM= VID / 2
to VCC- VID / 2, TA= -40°C to +105°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V, VCM= 1.2V, = +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUT (IN+, IN-)Differential Input High ThresholdVTH(Note 3)50mV
Differential Input Low ThresholdVTL(Note 3)-50mV
Input CurrentIIN+, IIN-PWRDWN = high or low (Note 3)-40+40µA
MAX9248/MAX9250ECM426078PWRDWN =
high or lowMAX9248/MAX9250GCM426088
MAX9248/MAX9250ECM426078Input Bias Resistor (Note 3)RIB
VCC_ =
0 or open,
PWRDWN =
0 or open,
Figure 1MAX9248/MAX9250GCM426088
Power-Off Input CurrentIINO+, IINO-VCC_ = 0 or open,
PWRDWN = 0 or open (Note 3)-60+60µA
POWER SUPPLY2.5MHz19RNG1 = low
RNG0 = low5MHz33
5MHz28RNG1 = low
RNG0 = high10MHz49
10MHz33RNG1 = high
RNG0 = low20MHz59
20MHz45
MAX9250
CL = 8pF,
worst-case
pattern,
Figure 2
RNG1 = high
RNG0 = high42MHz89
2.5MHz31RNG1 = low
RNG0 = low5MHz48
5MHz40RNG1 = low
RNG0 = high10MHz70
10MHz49RNG1 = high
RNG0 = low20MHz87
20MHz68
35MHz100
Worst-Case Supply Current
MAX9248
CL = 8pF,
worst-case
pattern,
Figure 2
RNG1 = high
RNG0 = high42MHz120
Power-Down Supply CurrentICCZ(Note 4)50µA
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
AC ELECTRICAL CHARACTERISTICS(VCC_= +3.0V to +3.6V, CL= 8pF, PWRDWN= high, differential input voltage VID= 0.1V to 1.2V, input common-mode voltage
VCM = VID / 2to VCC- VID / 2, TA= -40°C to +105°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V,
VCM= 1.2V, TA= +25°C.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFCLK TIMING REQUIREMENTS MAX9248/MAX9250ECM 23.8 400.0 Period tT
MAX9248/MAX9250GCM 28.6 400.0
ns
MAX9248/MAX9250ECM 2.5 42.0 Frequency fCLK MAX9248/MAX9250GCM 2.5 35.0 MHz
Frequency Variation fCLK REFCLK to serializer PCLK_IN,
worst-case output pattern (Figure 2) -2.0 +2.0 %
Duty Cycle DC 40 50 60 %
Transition Time tTRAN 20% to 80% 6 ns
SWITCHING CHARACTERISTICS MAX9248/
MAX9250ECM 2.2 4.6
RNG1 = high
MAX9248/
MAX9250GCM 2.2 4.9
MAX9248/
MAX9250ECM 2.8 5.2
Output Rise Time tR Figure 3
RNG1 = low MAX9248/
MAX9250GCM 2.8 6.1
ns
RNG1 = high MAX9248/
MAX9250ECM 1.9 4.0
MAX9248/
MAX9250ECM 2.3 4.3 Output Fall Time tR Figure 3
RNG1 = low
MAX9248/
MAX9250GCM 2.3 5.2
ns
PCLK_OUT High Time tHIGH Figure 4 0.4 x
tT
0.45 x
tT
0.6 x
tT ns
PCLK_OUT Low Time tLOW Figure 4 0.4 x
tT
0.45 x
tT
0.6 x
tT ns
Data Valid Before PCLK_OUT tDVB Figure 5 0.35 x tT 0.4 x ns
Data Valid After PCLK_OUT tDVA Figure 5 0.35 x tT 0.4 x ns
MAX9248, Figure 8
33,600 x tT PLL Lock to REFCLK tPLLREF MAX9250, Figure 7
16,928 x tT ns
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTHandVTL.
Note 2:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4:All LVTTL/LVCMOS inputs, except PWRDWNat ≤0.3V or ≥VCC- 0.3V. PWRDWNis ≤0.3V, REFCLK is static.
Note 5:CLincludes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS (continued)(VCC_= +3.0V to +3.6V, CL= 8pF, PWRDWN= high, differential input voltage VID= 0.1V to 1.2V, input common-mode voltage
VCM = VID / 2to VCC- VID / 2, TA= -40°C to +105°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V,
VCM= 1.2V, TA= +25°C.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum output
frequency
fREFCLK
+ 3.6%
fREFCLK
+ 4.0%
fREFCLK
+ 4.4% SS = high,
Figure 11 Minimum output
frequency
fREFCLK
- 4.4%
fREFCLK
- 4.0%
fREFCLK
- 3.6%
Maximum output
frequency
fREFCLK
+ 1.8%
fREFCLK
+ 2.0%
fREFCLK
+ 2.2%
Spread-Spectrum Output
Frequency (MAX9248) fPCLK_OUT
SS = low,
Figure 11 Minimum output
frequency
fREFCLK
- 2.2%
fREFCLK
- 2.0%
fREFCLK
- 1.8%
MHz
Spread-Spectrum Modulation
Frequency fSSM Figure 11 fREFCLK /
1024 kHz
Power-Down Delay tPDD Figures 7, 8 100 ns
SS Change Delay tSSPLL MAX9248, Figure 17 32,800
x tT ns
Output Enable Time tOE MAX9250, Figure 8 10 30 ns
Output Disable Time tOZ MAX9250, Figure 9 10 30 ns
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCYMAX9248/50 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)30510152025
MAX9248
MAX9250
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)MAX9248/50 toc02
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
RNG1 = HIGH
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)MAX9248/50 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
RNG1 = LOW
OUTPUT POWER SPECTRUM vs. FREQUENCY
(REFCLK = 42MHz, NO SPREAD,4%, AND 2% SPREAD)MAX9248/50 toc04
FREQUENCY (MHz)
POWER SPECTRUM (dBm)44424140
NO SPREADRESOLUTION BW = 30kHz
VIDEO BW = 100kHz
2% SPREAD
4% SPREAD
BIT-ERROR RATE vs. CABLE LENGTHMAX9248/50 toc05
CAT5 CABLE LENGTH (m)
BIT-ERROR RATE
1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
REFCLK = 42MHz
840Mbps DATA RATE
FOR CABLE LENGTH < 10m
BER < 10-12
CAT5 CABLE
CABLE LENGTH vs. FREQUENCY
BIT-ERROR RATE < 10-9MAX9248/50 toc06
CABLE LENGTH (m)
FREQUENCY (MHz)161412108642020
Typical Operating Characteristics(VCC_ = +3.3V, CL= 8pF, TA= +25°C, unless otherwise noted.)
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
Pin Description
PIN
MAX9248MAX9250NAMEFUNCTIONR/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT
for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a
falling latch edge. Internally pulled down to GND.2RNG1LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internally pulled down to GND.VCCLVDSLV D S S up p l y V ol tag e. Byp ass to LV D S G N D w i th 0.1µF and 0.001µF cap aci tor s i n p ar al l el as
cl ose to the d evi ce as p ossi b l e, w i th the sm al l est val ue cap aci tor cl osest to the sup p l y p i n.4IN+Noninverting LVDS Serial-Data Input5IN-Inverting LVDS Serial-Data InputLVDSGNDLVDS Supply Ground7PLLGNDPLL Supply GroundVCCPLLPLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.9RNG0LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internal pulldown to GND.10GNDDigital Supply Ground11VCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to
GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with
the smallest value capacitor closest to the supply pin.12REFCLKLVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the
serializer PCLK_IN frequency. Internally pulled down to GND.13PWRDWNLVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.—SSLV TTL/LV C M OS S p r ead - S p ectr um Inp ut. S S sel ects the fr eq uency sp r ead of P C LK_O U T and
outp ut d ata r el ati ve to P C LK_IN . D r i ve S S hi g h for 4% sp r ead and p ul l l ow for 2% sp r ead .
15–2315–23CNTL_OUT0–
CNTL_OUT8
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the
rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held
at the last state when DE_OUT is high.24DE_OUTLVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low
indicates CNTL_OUT[8:0] are active.
25, 3725, 37VCCOGNDOutput Supply Ground
26, 3826, 38VCCOOutput Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250
Functional DiagramIN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
RGB_OUT
LOCK
PWRDWN
PCLK_OUT
DE_OUT
CNTL_OUT
SSPLL
FIFO
RNG[0:1]
R/F
RNG[0:1]
IN+
IN-
REFCLK
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
R/F
MAX9250MAX9248
Pin Description (continued)
PIN
MAX9248MAX9250NAMEFUNCTION27LOCKLVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.28PCLK_OUTLV TTL/LV C M OS P ar al lel Cl ock Outp ut. Latches d ata i nto the next chi p on the ed g e selected b y R/F.
29–36,
29–36,
RGB_OUT0–
RBG_OUT7,
RGB_OUT8–
RGB_OUT17
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are
latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high,
and are held at the last state when DE_OUT is low.14OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving
low places the single-ended outputs in high impedance except LOCK. Internally pulled
down to GND.
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250PCLK_OUT
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
tDVBtDVA
2.0V
2.0V2.0V
0.8V
0.8V0.8V
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
Figure 5. Synchronous Output Timing
IN+, IN-
PCLK_OUT
CNTL_OUT
RGB_OUT
20 SERIAL BITS
SERIAL-WORD NSERIAL-WORD N + 1
PARALLEL-WORD N - 1PARALLEL-WORD N
tDELAY
PCLK_OUT SHOWN FOR R/F = HIGH
PCLK_OUT
tLOW
tHIGH
2.0V
0.8V
Figure 4. High and Low Times
DE_OUT
LOCK
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.9 x VCCO
0.1 x VCCOtR
Figure 3. Output Rise and Fall Times
LVDS
RECEIVER
1.2V
IN+
RIB
RIB
IN-
Figure 1. LVDS Input Bias
PCLK_OUT
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
MAX9248/MAX9250PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
tPLLREFTRANSITION
WORD
FOUND
RECOVERED CLOCK
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
tPDD
0.8V
2.0V
Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250
PWRDWN
REFCLK
PCLK_OUT
RGB_OUT
CNTL_OUT
DE_OUT
LOCK
tPLLREFTRANSITION
WORD
FOUND
OUTPUT CLOCK SPREAD
CLOCK STRETCH
VALID DATA
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
NOTE: R/F = HIGH
tPDD
0.8V
2.0V
288 CLOCK CYCLES
OUTPUT DATA SPREAD
Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248
