MAX9234EUM+TD ,Hot-Swappable, 21-Bit, DC-Balanced LVDS DeserializersApplicationsOrdering InformationAutomotive Navigation SystemsAutomotive DVD Entertainment SystemsPI ..
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MAX923CSA ,Ultra Low-Power, Single/Dual-Supply ComparatorsFeaturesThe MAX921–MAX924 single, dual, and quad micro-' µMAX Package—Smallest 8-Pin SOpower, low-v ..
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I Full or Hall Duplex
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MAX9234EUM+TD
Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers
MAX9234/MAX9236/
MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
General DescriptionThe MAX9234/MAX9236/MAX9238 deserialize three
LVDS serial-data inputs into 21 single-ended
LVCMOS/LVTTL outputs. A parallel-rate LVDS clock
received with the LVDS data streams provides timing for
deserialization. The outputs have a separate supply,
allowing 1.8V to 5V output logic levels. All these devices
are hot-swappable and allow “on-the-fly” frequency
programming.
The MAX9234/MAX9236/MAX9238 feature DC balance,
which allows isolation between a serializer and deseri-
alizer using AC-coupling. Each deserializer decodes
data transmitted by one of the MAX9209/MAX9211/
MAX9213/MAX9215 serializers.
The MAX9234 has a rising-edge output strobe. The
MAX9236/MAX9238 have a falling-edge output strobe.
The MAX9234/MAX9236/MAX9238 operate in DC-
balanced mode only.
The MAX9234/MAX9236 operate with a parallel input
clock of 8MHz to 34MHz, while the MAX9238 operates
from 16MHz to 66MHz. The transition time of the single-
ended outputs is increased on the low-frequency version
parts (MAX9234/MAX9236) for reduced EMI. The LVDS
inputs meet ISO 10605 ESD specification, ±25kV for Air-
Gap Discharge and ±8kV Contact Discharge.
The MAX9234/MAX9236/MAX9238 are available in 48-pin
TSSOP packages and operate over the -40°C to +85°C
temperature range.
ApplicationsAutomotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
FeaturesDC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage RangeOn-the-Fly Frequency ProgrammingOperating Frequency Range
8MHz to 34MHz (MAX9234/MAX9236)
16MHz to 66MHz (MAX9238)Falling-Edge Output Strobe (MAX9236/MAX9238)Slower Output Transitions for Reduced EMI
(MAX9234/MAX9236)High-Impedance Outputs when PWRDWNIs Low
Allow Output Busing5V-Tolerant PWRDWNInputPLL Requires No External ComponentsUp to 1.386Gbps ThroughputSeparate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V LogicLVDS Inputs Meet ISO 10605 ESD RequirementsLVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
StandardLow-Profile, 48-Lead TSSOP Package+3.3V Main Power Supply-40°C to +85°C Operating Temperature Range
Ordering Information
Functional Diagram and Pin Configuration appear at end of
data sheet.
PARTTEMP RANGEPIN-
PACKAGE
MAX9234EUM+-40°C to +85°C48 TSSOP
MAX9234EUM/V+-40°C to +85°C48 TSSOP
MAX9236EUM+-40°C to +85°C48 TSSOP
MAX9238EUM+-40°C to +85°C48 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V Denotes an automotive qualified part.
Note:Devices are also available in a tape-and-reel packaging.
Specify tape and reel by adding “T” to the part number when
ordering.
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, VCCO= +3.0V to +5.5V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-
mode voltage VCM= VID/2to 2.4V - VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= VCCO=
+3.3V, VID= 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.5V to +4.0V
VCCOto GND.........................................................-0.5V to +6.0V
RxIN_, RxCLK IN_ to GND....................................-0.5V to +4.0V
PWRDWNto GND....................................................-0.5V to 6.0V
RxOUT_, RxCLK OUT to GND................-0.5V to (VCCO + 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C).......1282mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND..................................………………….±5kV
IEC 61000-4-2 (RD= 330Ω, CS = 150pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND.........±8kV
Air-Gap Discharge (RxIN_, RxCLK IN_) to GND.......±15kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND ........±8kV
Air Discharge (RxIN_, RxCLK IN_) to GND ...............±25kV
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUT (PWRDWN)High-Level Input VoltageVIH2.05.5V
Low-Level Input VoltageVIL-0.3+0.8V
Input CurrentIINVIN = high or low-70+70µA
Input Clamp VoltageVCLICL = -18mA-1.5V
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT)IOH = -100µAVCCO -
RxCLK OUTVCCO -
0.25MAX9234/
MAX9236
RxOUT_VCCO -
High-Level Output VoltageVOH
IOH = -2mA
MAX9238VCCO -
IOL = 100µA0.1
RxCLK OUT 0.2MAX9234/
MAX9236RxOUT_0.26Low-Level Output VoltageVOLIOL = 2mA
MAX92380.2
High-Impedance Output CurrentIOZPWRDWN = low,
VOUT_ = -0.3V to VCCO + 0.3V-20+20µA
RxCLK OUT-10-40MAX9234/
MAX9236RxOUT_-5-20VCCO = 3.0V to
3.6V, VOUT = 0VMAX9238-10-40
RxCLK OUT-28-75MAX9234/
MAX9236RxOUT_-14-37
Output Short-Circuit Current
(Note: Short one output at a
time.)IOS
VCCO = 4.5V to
5.5V, VOUT = 0V
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, VCCO= +3.0V to +5.5V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-
mode voltage VCM= VID/2to 2.4V - VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= VCCO=
+3.3V, VID= 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVDS INPUTSDifferential Input-High ThresholdVTH50mV
Differential Input-Low ThresholdVTL-50mV
Input CurrentIIN+, IIN-PWRDWN = high or low-25+25µA
Power-Off Input CurrentIINO+, IINO-VCC = VCCO = 0V or open,
PWRDWN = 0V or open-40+40µA
PWRDWN = high or low (Figure 1)Input Resistor 1RIN1VCC = VCCO = 0V or open (Figure 1)4278kΩ
POWER SUPPLY8MHz42
16MHz57MAX9234/
MAX9236
34MHz98
16MHz63
34MHz106
Worst-Case Supply CurrentICCW
CL = 8pF,
worst-case
pattern; VCC =
VCCO = 3.0V to
3.6V, Figure 2MAX9238
66MHz177
Power-Down Supply CurrentICCZPWRDWN = low50µA
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTHandVTL.
Note 2:Maximum and minimum limits overtemperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4:CLincludes probe and test jig capacitance.
Note 5:RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.
Note 6:RSKM measured with ≤150ps cycle-to-cycle jitter on RxCLK IN.
AC ELECTRICAL CHARACTERISTICS(VCC= VCCO= +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL= 8pF, PWRDWN= high, differential input voltage VID=
0.1V to 1.2V, input common mode voltage VCM= VID/2to 2.4V - VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical
values are at VCC= VCCO= +3.3V, VID= 0.2V, VCM= 1.25V, TA= +25°C.) (Notes 3, 4, 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRxOUT3.525.046.24MAX9234/
MAX9236RxCLK OUT2.23.153.9Output Rise TimeCLHT
0.1VCCO to
0.9VCCO,
Figure 3MAX92382.23.153.9
RxOUT1.953.184.35MAX9234/
MAX9236RxCLK OUT1.32.122.9Output Fall TimeCHLT
0.9VCCO to
0.1VCCO,
Figure 3MAX92381.32.122.9
8MHz66007044
16MHz25603137
34MHz9001327RxIN Skew MarginRSKMFigure 4
(Note 6)
MAX923866MHz330685
RxCLK OUT High TimeRCOHFigures 5a, 5b0.35 x
RCOPns
RxCLK OUT Low TimeRCOLFigures 5a, 5b0.35 x
RCOPns
RxOUT Setup to RxCLK OUTRSRCFigures 5a, 5b0.30 x
RCOPns
RxOUT Hold from RxCLK OUTRHRCFigures 5a, 5b0.45 x
RCOPns
RxCLK IN to RxCLK OUT DelayRCCDFigures 6a, 6b4.96.178.1ns
Deserializer Phase-Locked Loop
SetRPLLSFigure 732800
x RCIPns
Deserializer Power-Down DelayRPDDFigure 8100ns
MAX9234/MAX9236
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCYMAX9234/6/8 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)25201510
WORST CASE
27 - 1 PRBS
MAX9238
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCYMAX9234/6/8 toc02
FREQUENCY (MHz)
SUPPLY CURRENT (mA)50403020
WORST CASE
27 - 1 PRBS
MAX9234/MAX9236
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)MAX9234/6/8 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
CLHT
CHLT
MAX9238
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)MAX9234/6/8 toc04
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
CLHT
CHLT
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Typical Operating Characteristics(VCC= VCCO= +3.3V, CL= 8pF, PWRDWN= high, differential input voltage VID= 0.2V, input common-mode voltage VCM= 1.2V,= +25°C, unless otherwise noted.)
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Pin Description
PINNAMEFUNCTION1, 2, 4, 5, 45,
46, 47RxOUT14–RxOUT20Channel 2 Single-Ended Outputs
3, 25, 32, 38,GNDGroundN.C.No Connection
7, 13, 18LVDS GNDLVDS GroundRxIN0-Inverting Channel 0 LVDS Serial-Data InputRxIN0+Noninverting Channel 0 LVDS Serial-Data InputRxIN1-Inverting Channel 1 LVDS Serial-Data InputRxIN1+Noninverting Channel 1 LVDS Serial-Data InputLVDS VCCLVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to LVDS VCC as possible, with the smallest value capacitor closest to the supply pin.RxIN2-Inverting Channel 2 LVDS Serial-Data InputRxIN2+Noninverting Channel 2 LVDS Serial-Data InputRxCLK IN-Inverting LVDS Parallel Rate Clock InputRxCLK IN+Noninverting LVDS Parallel Rate Clock Input
19, 21PLL GNDPLL GroundPLL VCCPLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as
close to PLL VCC as possible, with the smallest value capacitor closest to the supply pin.PWRDWN5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are
high impedance when PWRDWN = low or open.RxCLK OUTParallel Rate Clock Single-Ended Output. The MAX9234 has a rising-edge strobe. The
MAX9236/MAX9238 have a falling-edge strobe.
24, 26, 27, 29,
30, 31, 33RxOUT0–RxOUT6Channel 0 Single-Ended Outputs
28, 36, 48VCCOOutput Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to VCCO as possible, with the smallest value capacitor closest to the supply pin.
34, 35, 37, 39,
40, 41, 43RxOUT7–RxOUT13Channel 1 Single-Ended OutputsVCCDigital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close
to VCC as possible, with the smallest value capacitor closest to the supply pin.
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Detailed DescriptionThe MAX9234/MAX9236 operate at a parallel clock fre-
quency of 8MHz to 34MHz. The MAX9238 operates at a
parallel clock frequency of 16MHz to 66MHz. The tran-
sition times of the single-ended outputs are increased
on the MAX9234/MAX9236 for reduced EMI.
DC BalanceData coding by the MAX9209/MAX9211/MAX9213/
MAX9215 serializers (which are companion devices to
the MAX9234/MAX9236/MAX9238 deserializers) limits
the imbalance of ones and zeros transmitted on each
channel. If +1 is assigned to each binary 1 transmitted
and -1 is assigned to each binary 0 transmitted, the varia-
tion in the running sum of assigned values is called the
digital sum variation (DSV). The maximum DSV for the
data channels is 10. At most, 10 more zeros than ones,
or 10 more ones than zeros, are transmitted. The maxi-
mum DSV for the clock channel is five. Limiting the DSV
and choosing the correct coupling capacitors maintains
differential signal amplitude and reduces jitter due to
droop on AC-coupled links.
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9234/
MAX9236/MAX9238 deserializers whether the data bits
are inverted (see Figure 9). The deserializer restores
the original state of the parallel data. The LVDS clock
signal alternates duty cycles of 4/9 and 5/9, which
maintain DC balance.
AC-Coupling BenefitsBit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
the voltage rating of the capacitor. The typical LVDS dri-
ver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately ±1V common-mode differ-
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling.
However, two capacitors—one at the serializer output
and one at the deserializer input—provide protection in
case either end of the cable is shorted to a high voltage.
RIN1
RxIN_ + OR
RxCLK IN+
RxIN_ - OR
RxCLK IN-
RIN1
1.2V
Figure 1. LVDS Input Circuit
RCIP
RxCLK OUT
ODD RxOUT
EVEN RxOUT
RISING-EDGE STROBE SHOWN.
Table 1. Part Equivalent Table
PARTEQUIVALENT WITH DCB/NC = HIGH OR OPENOPERATING
FREQUENCY (MHz)OUTPUT STROBEMAX9234MAX92108 to 34Rising edge
MAX9236MAX92208 to 34Falling edge
MAX9238MAX922216 to 66Falling edge
MAX9234/MAX9236/MAX9238
Hot-Swappable, 21-Bit, DC-Balanced LVDS
DeserializersIDEAL
MINMAX
INTERNAL STROBE
IDEAL
RSKMRSKM
IDEAL SERIAL BIT TIME
1.3V
1.1V
Figure 4. LVDS Receiver Input Skew Margin
RxOUT_
RxCLK OUT
RCIP
RCOHRCOL
2.0V
0.8V
2.0V
0.8V
2.0V2.0V2.0V
0.8V 0.8V
RHRCRSRC
Figure 5a. MAX9234 Output Setup/Hold and High/Low Times
RxOUT_
RxCLK OUT
RCIP
RCOHRCOL
2.0V
0.8V
2.0V
0.8V
2.0V2.0V
0.8V0.8V0.8V
RHRCRSRC
Figure 5b. MAX9236/MAX9238 Output Setup/Hold and High/Low
VID = 0
1.5V
RCCD
RxCLK IN
RxCLK OUT
Figure 6a. MAX9234 Clock-IN to Clock-OUT Delay
RxCLK IN
RxCLK OUT
RCCD
1.5V
VID = 0
Figure 6b. MAX9236/MAX9238 Clock-IN to Clock-OUT Delay
90%90%
10%10%
CHLTCLHT
RxOUT_ OR
RxCLK OUTRxOUT_ OR
RxCLK OUT
8pF
Figure 3. Output Load and Transition Times
PWRDWN
VCC
RxCLK IN
RxCLK OUT
RPLLS
HIGH-Z
Figure 7. Phase-Locked Loop Set Time
