MAX9218ECM+-MAX9218ECM+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX9218ECM+-MAX9218ECM+T
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
General Description
The MAX9218 digital video serial-to-parallel converter
deserializes a total of 27 bits during data and control
phases. In the data phase, the LVDS serial input is con-
verted to 18 bits of parallel video data and in the control
phase, the input is converted to 9 bits of parallel control
data. The separate video and control phases take
advantage of video timing to reduce the serial data rate.
The MAX9218 pairs with the MAX9217 serializer to form
a complete digital video transmission system.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9218 features a selec-
table rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9218 operates from a +3.3V core supply and
features a separate output supply for interfacing to 1.8V
to 3.3V logic-level inputs. This device is available in 48-
lead Thin QFN and LQFP packages and is specified
from -40°C to +85°C.
Applications
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
FeaturesProprietary Data Decoding for DC Balance and
Reduced EMIControl Data Deserialized During Video BlankingFive Control Data Inputs Are Single Bit-ErrorTolerantOutput Transition Time Is Scaled to OperatingFrequency for Reduced EMIStaggered Output Switching Reduces EMIOutput Enable Allows Busing of OutputsClock Pulse Stretch on LockWide ±2% Reference Clock ToleranceSynchronizes to MAX9217 Serializer WithoutExternal ControlISO 10605 ESD ProtectionSeparate Output Supply Allows Interface to 1.8V
to 3.3V Logic+3.3V Core Power SupplySpace-Saving Thin QFN and LQFP Packages-40°C to +85°C Operating Temperature
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
DE_OUT
CNTL_OUT8
CNTL_OUT7
CNTL_OUT6
CNTL_OUT5
CNTL_OUT4
CNTL_OUT3
CNTL_OUT2
CNTL_OUT1T
CNTL_OUT0
OUTEN
PWRDWN
VCCOGND
VCCO
RGB_OUT8
RGB_OUT9
RGB_OUT10
RGB_OUT11
RGB_OUT12
RGB_OUT13
RGB_OUT14
RGB_OUT15
RGB_OUT16
RGB_OUT17
LQFP
MAX92183534333231302928272625
RGB_OUT7RGB_OUT6RGB_OUT5RGB_OUT4RGB_OUT3RGB_OUT2RGB_OUT1RGB_OUT0PCLK_OUTLOCKVCCOVCCO
GND
R/F
RNG1
CCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
GND
REFCLK
RGB_OUT7RGB_OUT6RGB_OUT4RGB_OUT3RGB_OUT0PCLK_OUTLOCKV
CCO
GND
CCO
RGB_OUT2RGB_OUT1RGB_OUT5
TOP VIEW
CCLVDS
IN+
IN-
LVDS GND
PLL GND
VCCPLL
RNG0
REFCLK
GND
RNG1
R/F
DE_OUT
CNTL_OUT8
CNTL_OUT6
CNTL_OUT5
CNTL_OUT2
CNTL_OUT1
CNTL_OUT0
PWRDWN
OUTEN
CNTL_OUT4
CNTL_OUT3
CNTL_OUT7RGB_OUT8
RGB_OUT9
RGB_OUT10
RGB_OUT11
RGB_OUT12
RGB_OUT13
RGB_OUT14
RGB_OUT17
RGB_OUT15
VCCO
VCCO GND37
THIN QFN-EP
MAX92183534333231302928272625234567891112234567891112
RGB_OUT16
PARTTEMP RANGEPIN-PACKAGE
MAX9218ECM+-40°C to +85°C48 LQFP
MAX9218ECM/V+-40°C to +85°C48 LQFP
MAX9218ETM+-40°C to +85°C48 Thin QFN-EP*
Pin Configurations
Ordering Information
19-3557; Rev 5; 8/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-mode voltage VCM= VID/2
to VCC- VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V, VCM= 1.2V, = +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC_to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
IN+, IN- to LVDS GND...........................................-0.5V to +4.0V
IN+, IN- Short Circuit to LVDS GND or VCCLVDS......Continuous
IN+, IN- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
(R/F, OUTEN, RNG_, REFCLK,
PWRDWN) to GND.................................-0.5V to (VCC+ 0.5V)
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to VCCOGND...........................-0.5V to (VCCO+ 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C)....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C).2963mW
ESD Protection
Machine Model (RD= 0Ω, CS= 200pF)
All Pins to GND...........................................................±200V
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND..........................................................±3.0kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (IN+, IN-) to GND............................±10kV
Air Discharge (IN+, IN-) to GND....................................±30kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN)
High-Level Input VoltageVIH2.0VCC + 0.3V
Low-Level Input VoltageVIL-0.3+0.8V
Input CurrentIINVIN = -0.3V to (VCC + 0.3V),
PWRDWN = high or low-70+70µA
Input Clamp VoltageVCLICL = -18mA-1.5V
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
IOH = -100µAVCCO - 0.1
IOH = -2mA,
RNG1, RNG0 = highVCCO - 0.35High-Level Output VoltageVOH
IOH = -2mA, RNG1, RNG0 both not high
simultaneouslyVCCO - 0.4
IOL = 100µA0.1
IOL = 2mA,
RNG1, RNG0 = high0.3Low-Level Output VoltageVOL
IOL = 2mA, RNG1, RNG0 both not high
simultaneously0.35
High-Impedance Output CurrentIOZPWRDWN = low or OUTEN = low,
VO = -0.3V to VCCO + 0.3V-10+10µA
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC_= +3.0V to +3.6V, PWRDWN= high, differential input voltage VID= 0.05V to 1.2V, input common-mode voltage VCM= VID/2
to VCC- VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V, VCM= 1.2V, = +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
RNG1, RNG0 = high, VO = 0-10-50
Output Short-Circuit CurrentIOSRNG1, RNG0 both not high
simultaneously, VO = 0-7-40mA
LVDS INPUT (IN+, IN-)
Differential Input High ThresholdVTH50mV
Differential Input Low ThresholdVTL-50mV
Input CurrentIIN+, IIN-PWRDWN = high or low-20+20µA
PWRDWN = high or low355065kΩ
Input Bias ResistorRIBVCC_ = 0 or open,
PWRDWN = 0 or open, Figure 1355065kΩ
Power-Off Input CurrentIINO+, IINO-VCC_ = 0 or open,
PWRDWN = 0 or open-40+40µA
POWER SUPPLY
3MHz20RNG1 = low,
RNG0 = low7MHz35
7MHz25RNG1 = high,
RNG0 = low15MHz47
15MHz37
Worst-Case Supply CurrentICCW
CL = 8pF,
worst-case
pattern,
Figure 2RNG1 = high,
RNG0 = high35MHz70
Power-Down Supply CurrentICCZ(Note 3)50µA
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Note 1:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTHandVTL.
Note 2:Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:All LVTTL/LVCMOS inputs, except PWRDWNat ≤0.3V or ≥VCC- 0.3V. PWRDWNis ≤0.3V.
Note 4:AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5:CLincludes probe and test jig capacitance.
AC ELECTRICAL CHARACTERISTICS
(VCC_= +3.0V to 3.6V, CL= 8pF, PWRDWN= high, differential input voltage VID= 0.1V to 1.2V, input common-mode voltage
VCM = VID/2to VCC- VID/2, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC_= +3.3V, VID= 0.2V, VCM=
1.2V, TA= +25°C.) (Notes 4, 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REFCLK TIMING REQUIREMENTS
PeriodtT28.57333.00ns
FrequencyfCLK335MHz
Frequency VariationΔfCLKREFCLK to serializer PCLK_IN-2.0+2.0%
Duty CycleDC405060%
Transition TimetTRAN20% to 80%6ns
SWITCHING CHARACTERISTICS
RNG1, RNG0 = high3.24.4
Output Rise TimetRFigure 3RNG1, RNG0 both not high
simultaneously3.85.5ns
RNG1, RNG0 = high2.74.5
Output Fall TimetFFigure 3RNG1, RNG0 both not high
simultaneously3.65.3ns
PCLK_OUT High TimetHIGHFigure 40.4 x
0.45 x
0.6 xns
PCLK_OUT Low TimetLOWFigure 40.4 x
0.45 x
0.6 xns
Data Valid Before PCLK_OUTtDVBFigure 50.35 x tT0.4 x tTns
Data Valid After PCLK_OUTtDVAFigure 50.35 x tT0.4 x tTns
Input-to-Output DelaytDELAYFigure 6
2.575 x
tT +
2.725 x
tT +
PLL Lock to REFCLKtPLLREFFigure 716385 xns
Power-Down DelaytPDDFigure 7100ns
Output Enable TimetOEFigure 830ns
Output Disable TimetOZFigure 930ns
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
MAX9218 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)27711151923
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9218 toc02
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
RNG1 = RNG0 = HIGH
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9218 toc03
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
RNG1 = RNG0 = BOTH NOT HIGH
BIT-ERROR RATE
vs. CABLE LENGTH
MAX9218 toc04
CAT5e CABLE LENGTH (m)
BIT-ERROR RATE1284
35MHz CLOCK
700Mbps DATA RATE
FOR <12m, BER < 10-12
CAT5e
Typical Operating Characteristics
(VCC_ = +3.3V, CL= 8pF, TA= +25°C, unless otherwise noted.)
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Pin Description
PINNAMEFUNCTION
1R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for
latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch
edge. Internally pulled down to GND.RNG1LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internally pulled down to GND.
3VCCLVDSLVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.IN+Noninverting LVDS Serial Data InputIN-Inverting LVDS Serial Data InputLVDS GNDLVDS Supply GroundPLL GNDPLL Supply Ground
8VCCPLLPLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.RNG0LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internal pulldown to GND.GNDDigital Supply GroundVCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with
0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value
capacitor closest to the supply pin.REFCLKLVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer
PCLK_IN frequency. Internally pulled down to GND.PWRDWNLVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.OUTENLVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places
the single-ended outputs in high impedance. Internally pulled down to GND.
15–23CNTL_OUT [8:0]
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or
falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state
when DE_OUT is high.DE_OUTLVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates
CNTL_OUT[8:0] are active.
25, 37VCCO GNDOutput Supply Ground
26, 38VCCOOutput Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor closest to the supply pin.LOCKLVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.PCLK_OUTLVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
29–36,
39–48RGB_OUT [17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into
the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the
last state when DE_OUT is low.EPExposed Pad for Thin QFN Package Only. Connect to GND.
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Functional Diagram
IN+
IN-
RNG0
RNG1
MAX9218
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
R/F
OUTEN
RGB_OUT[17:0]
LOCK
PWRDWN
REFCLK
PCLK_OUT
DE_OUT
CNTL_OUT[8:0]
LVDS
RECEIVER
1.2V
IN+
RIB
RIB
IN-
Figure 1. LVDS Input Bias
PCLK_OUT
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern
DE_OUT
LOCK
PCLK_OUT
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.9VCCO
0.1VCCOtR
Figure 3. Output Rise and Fall Times
PCLK_OUT
tLOW
tHIGH
2.0V
0.8V
Figure 4. High and Low Times
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
PCLK_OUT
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
tDVBtDVA
2.0V
2.0V2.0V
0.8V
0.8V0.8V
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
Figure 5. Synchronous Output Timing
IN+, IN-
PCLK_OUT
CNTL_OUT
RGB_OUT
20 SERIAL BITSPCLK_OUT SHOWN FOR R/F = HIGH
SERIAL-WORD NSERIAL-WORD N + 1
PARALLEL-WORD N - 1PARALLEL-WORD N
tDELAY
Figure 6. Deserializer Delay

Partno	Mfg	Dc	Qty	Available	Descript
MAX9218ECM+ \|MAX9218ECM	MAX	N/a	10	avai	27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer
MAX9218ECM+T \|MAX9218ECMT	MAXIM	N/a	2691	avai	27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer