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MAX9217ECM+ |MAX9217ECMMAXIMN/a1000avai27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer
MAX9217ECM+ |MAX9217ECMMAXN/a470avai27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer
MAX9217ECM+T |MAX9217ECMTMAXIMN/a87avai27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer
MAX9217ETM+TMAXIMN/a27avai27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer


MAX9217ECM+ ,27-Bit, 3MHz-to-35MHz DC-Balanced LVDS SerializerELECTRICAL CHARACTERISTICS (continued)(V = +3.0V to +3.6V, R = 100Ω ±1%, PWRDWN = high, T = -40°C t ..
MAX9217ECM+ ,27-Bit, 3MHz-to-35MHz DC-Balanced LVDS SerializerApplicationsMAX9217ECM/V+ -40°C to +85°C 48 LQFPNavigation System DisplayMAX9217ETM+ -40°C to +85°C ..
MAX9217ECM+T ,27-Bit, 3MHz-to-35MHz DC-Balanced LVDS SerializerELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, R = 100Ω ±1%, PWRDWN = high, T = -40°C to +85°C, unl ..
MAX9217ETM+T ,27-Bit, 3MHz-to-35MHz DC-Balanced LVDS SerializerFeaturesThe MAX9217 digital video parallel-to-serial converter ♦ Proprietary Data Encoding for DC B ..
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MAX9217ECM+-MAX9217ECM+T-MAX9217ETM+T
27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer
General Description
The MAX9217 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial data rate. The data enable input determines
when the video or control data is serialized.
The MAX9217 pairs with the MAX9218 deserializer to
form a complete digital video serial link. Interconnect
can be controlled-impedance PCB traces or twisted-pair
cable. Proprietary data encoding reduces EMI and pro-
vides DC balance. DC balance allows AC-coupling,
providing isolation between the transmitting and receiv-
ing ends of the interface. The LVDS output is internally
terminated with 100Ω.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9217 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in 48-lead
Thin QFN and LQFP packages and is specified from
-40°C to +85°C.
Applications

Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
Features
Proprietary Data Encoding for DC Balance and
Reduced EMI
Control Data Sent During Video BlankingFive Control Data Inputs Are Single-Bit-Error
Tolerant
Output Common-Mode Filter Reduces EMIGreater than 10m STP Cable DriveWide ±2% Reference Clock ToleranceISO 10605 ESD ProtectionSeparate Input Supply Allows Interface to 1.8V to
3.3V Logic
+3.3V Core SupplySpace-Saving Thin QFN and LQFP Packages-40°C to +85°C Operating Temperature
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

RNG0RNG1V
CCLVDS
OUT+OUT-LVDS GNDLVDS GNDCMFPWRDWNV
CCPLL
PLL GNDI.C.
GND
CCIN
RGB_IN10RGB_IN11RGB_IN12RGB_IN13RGB_IN14RGB_IN15RGB_IN16RGB_IN17CNTL_IN0CNTL_IN1
RNG0RNG1V
CCLVDS
OUT+OUT-LVDS GNDLVDS GNDCMFPWRDWNV
CCPLL
PLL GNDI.C.
TOP VIEW
I.C.
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
VCC
GND
GND
VCC
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
GND
CCIN
RGB_IN10RGB_IN11RGB_IN12RGB_IN13RGB_IN14RGB_IN15RGB_IN16RGB_IN17CNTL_IN0CNTL_IN1
LQFP

MAX92173534333231302928272625234567891112
MAX92173534333231302928272625
I.C
PCLK_IN
DE_IN
CNTL_IN8
CNTL_IN7
CNTL_IN6
CNTL_IN5
CNTL_IN4
CNTL_IN3
CNTL_IN2
VCC
GND
GND
VCC
RGB_IN0
RGB_IN1
RGB_IN2
RGB_IN3
RGB_IN4
RGB_IN5
RGB_IN6
RGB_IN7
RGB_IN8
RGB_IN9
THIN QFN-EP
234567891112
PARTTEMP RANGEPIN-
PACKAGE

MAX9217ECM+-40°C to +85°C48 LQFP
MAX9217ECM/V+-40°C to +85°C48 LQFP
MAX9217ETM+-40°C to +85°C48 Thin QFN-EP*
Pin Configurations
Ordering Information

19-3558; Rev 4; 8/09
EVALUATION KIT
AVAILABLE

+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC_= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN= high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC_= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC_to _GND........................................................-0.5V to +4.0V
Any Ground to Any Ground...................................-0.5V to +0.5V
OUT+, OUT- to LVDS GND...................................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDS GND
or VCCLVDS.............................................................Continuous
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RGB_IN[17:0], CNTL_IN[8:0], DE_IN,
RNG0, RNG1, PCLK_IN,
PWRDWN, CMF to GND......................-0.5V to (VCCIN+ 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Lead LQFP (derate 21.7mW/°C above +70°C)....1739mW
48-Lead Thin QFN (derate 37mW/°C above +70°C).2963mW
ESD Protection
Machine Model (RD= 0Ω, CS= 200pF)
All Pins to GND..............................................................±200V
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND................................................................±2kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (OUT+, OUT-) to GND....................±10kV
Air Discharge (OUT+, OUT-) to GND............................±30kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_)

VCCIN = 1.71V to <3V0.65VCCINVCCIN + 0.3High-Level Input VoltageVIH2VCCIN + 0.3V
VCCIN = 1.71V to <3V-0.30.3VCCINLow-Level Input VoltageVIL-0.3+0.8V
Input CurrentIIN
VIN = -0.3V to (VCCIN + 0.3V),
VCCIN = 1.71V to 3.6V,
PWRDWN = high or low
-70+70µA
Input Clamp VoltageVCLICL = -18mA-1.5V
LVDS OUTPUTS (OUT+, OUT-)

Differential Output VoltageVODFigure 1250335450mV
Change in VOD Between
Complementary Output StatesΔVODFigure 120mV
Common-Mode VoltageVOSFigure 11.1251.291.375V
Change in VOS Between
Complementary Output StatesΔVOSFigure 120mV
Output Short-Circuit CurrentIOSVOUT+ or VOUT- = 0 or 3.6V-15±8+15mA
Magnitude of Differential Output
Short-Circuit CurrentIOSDVOD = 05.515mA
VOUT+ = 0,
VOUT- = 3.6VOutput High-Impedance CurrentIOZ
PWRDWN = low
VCC_ = 0VOUT+ = 3.6V,
VOUT- = 0+1µA
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
AC ELECTRICAL CHARACTERISTICS

(VCC_= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at VCC_= +3.3V, TA= +25°C.) (Note 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PCLK_IN TIMING REQUIREMENTS

Clock PeriodtTFigure 228.57333.00ns
Clock FrequencyfCLK335MHz
Clock Frequency Difference from
Deserializer Reference ClockΔfCLK-2+2%
Clock Duty CycleDCtHIGH/tT or tLOW/tT, Figure 2355065%
Clock Transition TimetR, tFFigure 22.5ns
SWITCHING CHARACTERISTICS

Output Rise TimetRISE20% to 80%, VOD ≥ 250mV,
modulation off, Figure 3215350ps
Output Fall TimetFALL80% to 20%, VOD ≥ 250mV,
modulation off, Figure 3206350ps
Input Setup TimetSETFigure 43ns
Input Hold TimetHOLDFigure 43ns
Serializer DelaytSDFigure 53.15 x
3.2 xns
PLL Lock TimetLOCKFigure 616385 xns
Power-Down DelaytPDFigure 71µs
DC ELECTRICAL CHARACTERISTICS (continued)

(VCC_= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN= high, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC_= +3.3V, TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Differential Output ResistanceRO78110147Ω
3MHz1525
5MHz1825
10MHz2328
20MHz3339
Worst-Case Supply CurrentICCW
RL = 100Ω ± 1%,
CL = 5pF,
continuous 10
transition words,
modulation off35MHz5070
Power-Down Supply CurrentICCZ(Note 3)50µA
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY

MAX9217 toc01
FREQUENCY (MHz)
SUPPLY CURRENT (mA)27231915117
Typical Operating Characteristics
(TA= +25°C, VCC_= +3.3V, RL= 100Ω, modulation off, unless otherwise noted.)
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
AC ELECTRICAL CHARACTERISTICS (continued)

(VCC_= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, TA= -40°C to +85°C, unless otherwise noted. Typical values
are at VCC_= +3.3V, TA= +25°C.) (Note 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

700Mbps data rate,
CMF open, Figure 82270
Peak-to-Peak Output Offset
VoltageVOSp-p
700Mbps data rate,
CMF 0.1µF to ground, Figure 81250
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD, ΔVOD, andΔVOS.
Note 2:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:
All LVTTL/LVCMOS inputs, except PWRDWNat ≤0.3V or ≥VCCIN- 0.3V. PWRDWNis ≤0.3V.
Note 4:
AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at ±6 sigma.
MAX9217
Pin Description
PINNAMEFUNCTION

1, 13, 37GNDInput Buffer Supply and Digital Supply Ground
2VCCINInput Buffer Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
3–10,
39–48RGB_IN[17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
11, 12, 15–21CNTL_IN[8:0]LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
14, 38VCCDigital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.DE_IN
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.PCLK_INLVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
24, 25I.C.Internally connected to GND. Connect to GND or leave unconnected.PLL GNDPLL Supply GroundVCCPLLPLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.PWRDWNLVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.CMFCommon-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
30, 31LVDS GNDLVDS Supply GroundOUT-Inverting LVDS Serial Data OutputOUT+Noninverting LVDS Serial Data OutputVCCLVDSLVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.RNG1LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.RNG0LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.EPExposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PCB GND.
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
Functional Diagram

MAX9217
TIMING AND CONTROL
DC BALANCE/
ENCODEINPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
OUT+
OUT-
CMF
PLL
PAR-TO-SER
OUT-
VOD
VOS
GND
RL / 2
RL / 2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
VOS(-)VOS(+)
((OUT+) + (OUT-)) / 2
VOS(-)
VOD(-)VOD(-)
VOD = 0V
ΔVOS = |VOS(+) - VOS(-)|
ΔVOD = |VOD(+) - VOD(-)|
VOD(+)
Figure 1. LVDS DC Output Load and Parameters
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

VILmax
tHIGH
tLOWtF
VIHmin
PCLK_IN
Figure 2. Parallel Clock Requirements
OUT-CL
OUT+
tFALL
20%20%
(OUT+) - (OUT-)
80%80%
tRISE
Figure 3. Output Rise and Fall Times
VIHmin
VIHminVIHmin
VILmaxVILmax
VILmax
PCLK_IN
RGB_IN[17:0]
CNTL_IN[8:0]
DE_IN
tHOLDtSET
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer

tSDBIT 0BIT 19
N + 3
EXPANDED TIME SCALE
N + 4NN + 1N + 2
N - 1
RGB_IN
CNTL_IN
PCLK_IN
OUT_
Figure 5. Serializer Delay
VOD = 0VHIGH-Z
VILmax
tLOCK
PWRDWN
(OUT+) - (OUT-)
PCLK_IN
Figure 6. PLL Lock Time
HIGH-Z
VILmax
tPD
PWRDWN
(OUT+) - (OUT-)
PCLK_IN
Figure 7. Power-Down Delay
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