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MAX9213EUM+ |MAX9213EUMMAXIMN/a107avaiProgrammable DC-Balanced 21-Bit Serializers
MAX9209EUM+DMAXIMN/a1avaiProgrammable DC-Balanced 21-Bit Serializers
MAX9209EUM+TD |MAX9209EUMTDMAXN/a2500avaiProgrammable DC-Balanced 21-Bit Serializers
MAX9213ETM+ |MAX9213ETMMAXIMN/a57avaiProgrammable DC-Balanced 21-Bit Serializers
MAX9213EUM+D |MAX9213EUMDMAXIMN/a116avaiProgrammable DC-Balanced 21-Bit Serializers


MAX9209EUM+TD ,Programmable DC-Balanced 21-Bit SerializersMAX9209/MAX921319-2828; Rev 5; 3/12Programmable DC-Balanced 21-Bit Serializers
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MAX9209EUM+D-MAX9209EUM+TD-MAX9213ETM+-MAX9213EUM+-MAX9213EUM+D
Programmable DC-Balanced 21-Bit Serializers
General Description
The MAX9209/MAX9213 serialize 21 bits of LVTTL/
LVCMOS parallel input data to three LVDS outputs. A
parallel rate clock on a fourth LVDS output provides
timing for deserialization.
The MAX9209/MAX9213 feature programmable DC bal-
ance, which allows isolation between the serializer and
deserializer using AC-coupling. The DC balance circuits
on each channel code the data, limiting the imbalance
of transmitted ones and zeros to a defined range. The
companion MAX9210/MAX9214 deserializers decode
the data. When DC balance is not programmed, the
serializers are compatible with non-DC-balanced, 21-bit
serializers such as the DS90CR215 and DS90CR217.
Two frequency ranges and two DC-balance default
conditions are available for maximum replacement flexi-
bility and compatibility with existing non-DC-balanced
serializers.
The MAX9209/MAX9213 are available in TSSOP and
space-saving TQFN packages.
Applications

Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
Programmable DC-Balanced or Non-DC-Balanced
Operation
DC Balance Allows AC-Coupling for Ground-Shift
Tolerance
As Low as 8MHz OperationPin Compatible with DS90CR215 and DS90CR217
in Non-DC-Balanced Mode
Integrated 110Ω(DC-Balanced) and 410Ω(Non-
DC-Balanced) Output Resistors
5V Tolerant LVTTL/LVCMOS Data InputsPLL Requires No External ComponentsUp to 1.785Gbps ThroughputLVDS Outputs Meet IEC 61000-4-2 and ISO 10605
Requirements
LVDS Outputs Conform to ANSI TIA/EIA-644
LVDS Standard
Low-Profile 48-Lead TSSOP and Space-Saving
TQFN Packages
-40°C to +85°C Operating Temperature Range+3.3V Supply
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
Ordering Information

19-2828; Rev 5; 3/12
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PARTTEMP. RANGEPIN-PACKAGE
MAX9209EUM+
-40°C to +85°C48 TSSOP
MAX9209EUM/V+-40°C to +85°C48 TSSOP
MAX9209GUM+-40°C to +105°C48 TSSOP
MAX9213ETM+
-40°C to +85°C48 TQFN-EP*
MAX9213EUM+-40°C to +85°C48 TSSOP
Pin Configurations appear at end of data sheet.

TxIN 0 - 2021
TIMING
CONTROLPARALLEL-TO-
SERIAL
CONVERTER
AND
DC-BALANCE
LOGIC
CLOCK
GENERATOR
PLL
7X OR 9X
LVDS DRIVER 0
LVDS DRIVER 1
LVDS DRIVER 2
LVDS CLK
TxOUT0+
TxOUT0-
TxOUT1+
TxOUT1-
TxOUT2+
TxOUT2-
TxCLK OUT+
TxCLK OUT-
DCB/NC
TxCLK IN
MAX9209
MAX9213
Functional Diagram
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN= high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.5V to +4.0V
LVDS Outputs (TxOUT_, TxCLK OUT_) to GND...-0.5V to +4.0V
5V Tolerant LVTTL/LVCMOS Inputs
(TxIN_, TxCLK IN, PWRDWN) to GND..............-0.5V to +6.0V
(DCB/NC) to GND......................................-0.5V to (VCC+ 0.5V)
LVDS Outputs (TxOUT_, TxCLK OUT_)
Short to GND and Differential Short.......................Continuous
Continuous Power Dissipation (multilayer board, TA= +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C).......1282mW
48-Pin TQFN (derate 40mW/°C above +70°C)..........3200mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND..............................................................±2kV
IEC 61000-4-2 (RD= 330Ω, CS= 150pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND..±15kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (TxOUT_, TxCLK OUT_) to GND....±8kV
Air Gap Discharge (TxOUT_, TxCLK OUT_) to GND..±25kV
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SINGLE-ENDED INPUTS (TxIN_, TxCLK IN, PWRDWN, DCB/NC)

TxIN_, TxCLK IN, PWRDWN2.05.5
High-Level Input VoltageVIHDCB/NC2.0VCC +
Low-Level Input VoltageVIL-0.3+0.8V
Input CurrentIINV IN = hi g h or l ow , P WRDWN = hi g h or l ow -20+20µA
Input Clamp VoltageVCLICL = -18mA-0.9-1.5V
LVDS OUTPUTS (TxOUT_, TxCLK OUT)

Differential Output VoltageVODFigure 1250350450mV
Change in VOD Between
Complementary Output States∆VODFigure 1225mV
Output Offset VoltageVOSFigure 11.1251.251.375V
Change in VOS Between
Complementary Output States∆VOSFigure 11030mV
VOUT+ or VOUT- = 0V or VCC,
non-DC-balanced mode-10±5.7+10
Output Short-Circuit CurrentIOS
VOUT+ or VOUT- = 0V or VCC,
DC-balanced mode-15±8.2+15
VOD = 0V, non-DC-balanced mode
(Note 3)5.710Magnitude of Differential Output
Short-Circuit CurrentIOSD
VOD = 0V, DC-balanced mode (Note 3)8.215110147DC-balanced mode-40°C to +105°C78110150
292410547Differential Output ResistanceRO
Non-DC-balanced
mode-40°C to +105°C292410564
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Output High-Impedance CurrentIOZPWRDWN = low or VCC = 0V,
VOUT+ = 0V or 3.6V, VOUT- = 0V or 3.6V-0.5±0.1+0.5µA
8MHz MAX92094054
16MHz MAX92094868
34MHz MAX92097190
16MHz MAX92134664
34MHz MAX92135987
DC-balanced mode,
worst-case pattern,
CL = 5pF, Figure 2
66MHz MAX921394108
10MHz MAX92093039
20MHz MAX92093753
33MHz MAX92094970
40MHz MAX92095675
20MHz MAX92133649
33MHz MAX92134562
40MHz MAX92134970
66MHz MAX92136889
Worst-Case Supply CurrentICCW
Non-DC-balanced
mode, worst-case
pattern, CL = 5pF,
Figure 2
85MHz MAX921383100
Power-Down Supply CurrentICCZPWRDWN = low1750µA
DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, PWRDWN= high, DCB/NC = high or low, unless otherwise noted. Typical values are at VCC
= +3.3V, TA= +25°C.) (Notes 1, 2)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC= +3.3V, TA= +25°C.) (Notes 4, 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

MAX9209150280400LVDS Low-to-High Transition
TimeLLHTFigure 3MAX9213150260350ps
MAX9209150280400LVDS High-to-Low Transition
TimeLHLTFigure 3MAX9213150260350ps
TxCLK IN Transition TimeTCITFigure 44ns
10MHz MAX9209N/7 x TCIP
- 0.25N/7 x TCIPN/7 x TCIP
+ 0.25
20MHz MAX9209N/7 x TCIP
- 0.15N/7 x TCIPN/7 x TCIP
+ 0.15
40MHz MAX9209N/7 x TCIP
- 0.1N/7 x TCIPN/7 x TCIP
+ 0.1
20MHz MAX9213N/7 x TCIP
- 0.25N/7 x TCIPN/7 x TCIP
+ 0.25
40MHz MAX9213N/7 x TCIP
- 0.15N/7 x TCIPN/7 x TCIP
+ 0.15
N = 0, 1, 2, 3,
4, 5, 6
non-DC-
balanced mode,
Figure 5 (Note 6)
85MHz MAX9213N/7 x TCIP
- 0.1N/7 x TCIPN/7 x TCIP
+ 0.1
8MHz MAX9209N/9 x TCIP
- 0.25N/9 x TCIPN/9 x TCIP
+ 0.25
16MHz MAX9209N/9 x TCIP
- 0.15N/9 x TCIPN/9 x TCIP
+ 0.15
34MHz MAX9209N/9 x TCIP
- 0.1N/9 x TCIPN/9 x TCIP
+ 0.1
16MHz MAX9213N/9 x TCIP
- 0.25N/9 x TCIPN/9 x TCIP
+ 0.25
34MHz MAX9213N/9 x TCIP
- 0.15N/9 x TCIPN/9 x TCIP
+ 0.15
Output Pulse PositionTPPosN
N = 0, 1, 2, 3,
4, 5, 6, 7, 8
DC-balanced
mode, Figure 6
(Note 6)
66MHz MAX9213N/9 x TCIP
- 0.1N/9 x TCIPN/9 x TCIP
+ 0.1
MAX9209/MAX9213
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY

MAX9209 toc01
SUPPLY CURRENT (mA)302010
WORST-CASE
PATTERN7 - 1 PRBS
MAX9209
DC-BALANCED MODE
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY

MAX9209 toc02
SUPPLY CURRENT (mA)40302010
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9209
NON-DC-BALANCED MODE
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY

MAX9209 toc03
SUPPLY CURRENT (mA)604530
WORST-CASE
PATTERN
27 - 1 PRBS
MAX9213
NON-DC-BALANCED MODE
Typical Operating Characteristics

(VCC= +3.3V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, TA= +25°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, DCB/NC = high or low, unless otherwise noted. Typical values
are at VCC= +3.3V, TA= +25°C.) (Notes 4, 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

TxCLK IN High TimeTCIHFigure 70.3 x TCIP0.7 x TC IP ns
TxCLK IN Low TimeTCILFigure 70.3 x TCIP0.7 x TC IP ns
TxIN to TxCLK IN SetupTSTCFigure 72.2ns
TxIN to TxCLK IN HoldTHTCFigure 70ns
Non-DC-balanced mode, Figure 83.54.56.0TxCLK IN to TxCLK OUT DelayTCCDDC-balanced mode, Figure 84.75.97.2ns
Serializer Phase-Locked Loop SetTPLLSFigure 932800 x
TCIPns
Serializer Power-Down DelayTPDDFigure 101450ns
TxCLK IN Cycle-to-Cycle Jitter
(Input Clock Requirement)TJIT2ns
Magnitude of Differential Output
VoltageVOD595Mbps data rate, worst-case
pattern250mV
Note 1:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD, ∆VOD, and∆VOS.
Note 2:
Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3:
Guaranteed by design.
Note 4:
TCIP is the period of TxCLK IN.
Note 5:
AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 6:
Pulse position TPPosN is characterized using 27- 1 PRBS data.
Programmable DC-Balanced
21-Bit Serializers
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
MAX9213
EYE DIAGRAM—DC-BALANCED MODE

MAX9209 TOC08
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
2m OF CAT-5
UTP CABLE7 - 1 PRBS PATTERN
100Ω TERMINATION
ALL-CHANNELS
SWITCHING
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE

MAX9209 TOC07
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
0V
DIFFERENTIAL
10m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
MAX9213
EYE DIAGRAM—DC-BALANCED MODE

MAX9209 TOC09
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
5m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
MAX9213
EYE DIAGRAM—DC-BALANCED MODE

MAX9209 TOC10
100mV/div
300ps/div
0V
DIFFERENTIAL
TxCLK IN = 66MHz AC-COUPLED
USING 0.1μF CAPACITORS
10m OF CAT-5
UTP CABLE
ALL-CHANNELS
SWITCHING
27 - 1 PRBS PATTERN
100Ω TERMINATION
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY

FREQUENCY (MHz)
SUPPLY CURRENT (mA)4530
WORST-CASE
PATTERN7 - 1 PRBS
MAX9213
DC-BALANCED MODE
MAX9209 toc04
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE

MAX9209 TOC05
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
27 - 1 PRBS PATTERN
100Ω TERMINATION
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
2m OF CAT-5
UTP CABLE
MAX9213
EYE DIAGRAM—NON-DC-BALANCED MODE

MAX9209 TOC06
100mV/div
300ps/div
TxCLK IN = 85MHz
DC-COUPLED
27 - 1 PRBS PATTERN
100Ω TERMINATION
0V
DIFFERENTIAL
ALL-CHANNELS
SWITCHING
5m OF CAT-5
UTP CABLE
Typical Operating Characteristics (continued)

(VCC= +3.3V, RL= 100Ω±1%, CL= 5pF, PWRDWN= high, TA= +25°C, unless otherwise noted.)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
Pin Description
PIN
TSSOPTQFNNAMEFUNCTION

1, 3, 4, 44, 45, 47, 48,38, 39, 41, 42, 43, 45, 46TxIN0–TxIN65V Tolerant LVTTL/LVCMOS Channel 0 Data Inputs.
Internally pulled down to GND.
2, 8, 14, 212, 8, 15, 44VCCDigital Supply Voltage
5, 11, 17, 24, 465, 11, 18, 40, 47GNDGround
6, 7, 9, 10, 12, 13, 151, 3, 4, 6, 7, 9, 48TxIN7–TxIN135V Tolerant LVTTL/LVCMOS Channel 1 Data Inputs.
Internally pulled down to GND.
16, 18, 19, 20, 22, 23, 2510, 12, 13, 14, 16, 17, 19TxIN14–TxIN205V Tolerant LVTTL/LVCMOS Channel 2 Data Inputs.
Internally pulled down to GND.20TxCLK IN5V Tolerant LVTTL/LVCMOS Parallel Rate Clock Input.
Internally pulled down to GND.21PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally
pulled down to GND. Outputs are high impedance when
PWRDWN = low or open.
28, 3022, 24PLL GNDPLL Ground23PLL VCCPLL Supply Voltage
31, 36, 4225, 30, 36LVDS GNDLVDS Ground26TxCLK OUT+Noninverting LVDS Parallel Rate Clock Output27TxCLK OUT-Inverting LVDS Parallel Rate Clock Output28TxOUT2+Noninverting Channel 2 LVDS Serial Data Output29TxOUT2-Inverting Channel 2 LVDS Serial Data Output31LVDS VCCLVDS Supply Voltage32TxOUT1+Noninverting Channel 1 LVDS Serial Data Output33TxOUT1-Inverting Channel 1 LVDS Serial Data Output34TxOUT0+Noninverting Channel 0 LVDS Serial Data Output35TxOUT0-Inverting Channel 0 LVDS Serial Data Output37DCB/NC
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9209: pulled up to VCC
MAX9213: pulled up to VCC
See Table 1.—EPExposed Paddle (TQFN Only). Solder to ground.
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers

VOS(-)VOS(+)VOS(-)
VOD(+)
VOD(-)VOD(-)
TxOUT_- OR TxCLK OUT-
TxOUT_+ OR TxCLK OUT+
∆VOS = |VOS(+) - VOS(-)|
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
∆VOD = |VOD(+) - VOD(-)|
TCIP
TxCLK IN
ODD TxIN
EVEN TxIN
TxOUT_+ OR
TxCLK OUT+CL
TxOUT_- OR
TxCLK OUT-
80%80%
20%20%
LLHTLHLT
(TxOUT_+) - (TxOUT_-) OR
(TxCLK OUT+) - (TxCLK OUT-)
Figure 2. Worst-Case Test Pattern
Figure 3. LVDS Output Load and Transition Times
Figure 1. LVDS Output DC Parameters
90%
10%
90%
10%
VIH
TxCLK INVIL
TCITTCIT
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
Detailed Description

The MAX9209 operates at a parallel clock frequency of
8MHz to 34MHz in DC-balanced mode and 10MHz to
40MHz in non-DC-balanced mode. The MAX9213 oper-
ates at a parallel clock frequency of 16MHz to 66MHz
in DC-balanced mode and 20MHz to 85MHz in non-
DC-balanced mode.
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB/NC pin (see Table 1). In non-DC-
balanced mode, each channel serializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are serialized every clock cycle (7 data bits + 2 DC-bal-
ance bits). The highest data rate in DC-balanced mode
for the MAX9213 is 66MHz x 9 = 594Mbps. In non-DC-
balanced mode, the maximum data rate is 85MHz x 7 =
595Mbps. A bit time is 1 divided by the data rate, for
example, 1 / 595Mbps = 1.68ns.
DC Balance

Through data coding, the DC-balance circuits limit the
imbalance of ones and zeros transmitted on each chan-
nel. If +1 is assigned to each binary one transmitted
and -1 is assigned to each binary zero transmitted, the
variation in the running sum of assigned values is
called the digital sum variation (DSV). The maximum
DSV for the MAX9209/MAX9213 data channels is 10. At
most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
channel is 5. Limiting the DSV and choosing the correct
coupling capacitors maintain differential signal amplitude
TxIN15TxIN14TxIN20TxIN19TxIN18TxIN17TxIN16TxIN15TxIN14
TxIN8TxIN7TxIN13TxIN12TxIN11TxIN10TxIN9TxIN8TxIN7
TxIN1TxIN0TxIN6TxIN5TxIN4TxIN3TxIN2TxIN1TxIN0
CYCLE N - 1CYCLE N
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TxCLK OUT
(DIFFERENTIAL)
TxOUT2
(SINGLE ENDED)
TxOUT1
(SINGLE ENDED)
TxOUT0
(SINGLE ENDED)
Figure 5. Non-DC-Balanced Mode LVDS Output Pulse Position Measurement
DEVICEDCB/NCOPERATING
MODE
OPERATING
FREQUENCY
(MHz)

High or openDC balanced8 to 34
MAX9209LowNon-DC
balanced10 to 40
High or openDC balanced16 to 66
MAX9213LowNon-DC
balanced20 to 85
Table 1. DC-Balance Programming
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