MAX9206EAI+T ,10-Bit Bus LVDS DeserializersApplicationssize.♦ Fast Pseudorandom LockThe MAX9206/MAX9208 receive serial data at450Mbps and 600M ..
MAX9207EAI+ ,10-Bit Bus LVDS SerializersFeaturesThe MAX9205/MAX9207 serializers transform 10-bit-♦ Standalone Serializer (vs. SERDES) Ideal ..
MAX9207EAI+T ,10-Bit Bus LVDS SerializersApplicationsThe MAX9205/MAX9207 transmit serial data at speeds♦ Wide Reference Clock Input Rangeup ..
MAX9208EAI+T ,10-Bit Bus LVDS DeserializersApplicationsMAX9206EAI/V+ -40°C to +85°C 28 SSOP 16 to 40Cellular Phone Base DSLAMsStationsMAX9208E ..
MAX9208EAI+T ,10-Bit Bus LVDS DeserializersFeaturesThe MAX9206/MAX9208 deserializers transform a high-♦ Stand-Alone Deserializer (vs. SerDes) ..
MAX9209EUM+D ,Programmable DC-Balanced 21-Bit SerializersApplications♦ Low-Profile 48-Lead TSSOP and Space-SavingAutomotive Navigation SystemsTQFN PackagesA ..
MB88347 ,R-2R TYPE 8-BIT D/A CONVERTER WITH OPERATIONAL AMPLIFIER OUTPUT BUFFERSFUJITSU SEMICONDUCTORDS04-13506-1EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FUJITSU SEMICONDUCTORDS04-13512-2EDATA SHEETLinear IC converterCMOSD/A Converter for Digital Tuning ..
MB88347LPFV ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FUJITSU SEMICONDUCTORDS04-13512-2EDATA SHEETLinear IC converterCMOSD/A Converter for Digital Tuning ..
MB88347LPFV ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MAX9206EAI+-MAX9206EAI+T-MAX9208EAI+T
10-Bit Bus LVDS Deserializers
General DescriptionThe MAX9206/MAX9208 deserializers transform a high-
speed serial bus low-voltage differential signaling
(BLVDS) data stream into 10-bit-wide parallel LVCMOS/
LVTTL data and clock. The deserializers pair with seri-
alizers such as the MAX9205/MAX9207, which gener-
ate a serial BLVDS signal from 10-bit-wide parallel
data. The serializer/deserializer combination reduces
interconnect, simplifies PCB layout, and reduces board
size.
The MAX9206/MAX9208 receive serial data at
450Mbps and 600Mbps, respectively, over board
traces or twisted-pair cables. These devices combine
frequency lock, bit lock, and frame lock to produce a
parallel-rate clock and word-aligned 10-bit data.
Serialization eliminates parallel bus clock-to-data and
data-to-data skew.
A power-down mode reduces typical supply current to
less than 600µA. Upon power-up (applying power or
driving PWRDNhigh), the MAX9206/MAX9208 estab-
lish lock after receiving synchronization signals or serial
data from the MAX9205/MAX9207. An output enable
allows the outputs to be disabled, putting the parallel
data outputs and recovered output clock into a high-
impedance state without losing lock.
The MAX9206/MAX9208 operate from a single +3.3V
supply and are specified for operation from -40°C to
+85°C. The MAX9206/MAX9208 are available in 28-pin
SSOP packages.
Applications
FeaturesStand-Alone Deserializer (vs. SerDes) Ideal for
Unidirectional LinksAutomatic Clock RecoveryAllow Hot Insertion and Synchronization Without
System InterruptionBLVDS Serial Input Rated for Point-to-Point and
Bus ApplicationsFast Pseudorandom LockWide Reference Clock Input Range
16MHz to 45MHz (MAX9206)
40MHz to 60MHz (MAX9208)High 720ps (p-p) Jitter Tolerance (MAX9206)Low 30mA Supply Current (MAX9206 at 16MHz)10-Bit Parallel LVCMOS/LVTTL OutputUp to 600Mbps Throughput (MAX9208)Programmable Output Strobe EdgePin Compatible to DS92LV1212A and
DS92LV1224
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers19-2130; Rev 2; 11/10
Ordering Information
PARTTEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
MAX9206EAI+-40°C to +85°C28 SSOP16 to 40
MAX9206EAI/V+-40°C to +85°C28 SSOP16 to 40
MAX9208EAI+-40°C to +85°C28 SSOP40 to 66
EVALUATION KIT AVAILABLE
Pin Configuration appears at end of data sheet.PCB OR TWISTED PAIR
TCLK
PLLPLLENREN
PWRDN
INPUT LATCH
PARALLEL-TO-SERIAL
OUTPUT LATCH
SERIAL-TO-PARALLEL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
RCLK
LOCK
SYNC 1
SYNC 2
OUT+
OUT-
RI+
RI-
100Ω100Ω
TCLK_R/F
RCLK_R/F
REFCLK
ROUT_IN_1010
BUS
LVDS
MAX9205
MAX9207
MAX9206
MAX9208
Typical Operating CircuitCellular Phone BaseStations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC to AGND, DGND................................-0.3V to +4V
RI+, RI- to AGND, DGND.........................................-0.3V to +4V
All Other Pins to DGND..............................-0.3V to DVCC+ 0.3V
ROUT_ Short-Circuit Duration (Note 1)......................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C)..........762mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Rating (Human Body Model, RI+, RI-).........................±8kV
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
DC ELECTRICAL CHARACTERISTICS(VAVCC= VDVCC= +3.0V to +3.6V, differential input voltage |VID|= 0.1V to 1.2V, common-mode voltage VCM= |VID/2|to 2.4V
- |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC= VDVCC= +3.3V, VCM= 1.1V, |VID|= 0.2V,=+25°C.) (Notes 2, 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY 16MHz 30 45 MAX9206 45MHz 57 75
40MHz 55 75 Supply Current ICC
CL = 15pF,
worst-case
pattern,
Figure 1 MAX9208
60MHz 80 100
mA
Power-Down Supply Current ICCXPWRDWN = low 1 mA
LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F,PWRDN)
High-Level Input Voltage VIH 2.0 VCC V
Low-Level Input Voltage VIL 0 0.8 V
Input Current IINVIN = 0V, VAVCC, or VDVCC -15 15 μA
LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK, LOCK)High-Level Output Voltage VOH IOH = -5mA 2.2 2.9 VCC V
Low-Level Output Voltage VOL IOL = 5mA 0 0.33 0.5 V
Output Short-Circuit Current IOS VROUT_ = 0V -15 -38 -85 mA
Output High-Impedance Current IOZPWRDN = low, VROUT_ = VRCLK = V LOCK
= 0V, VAVCC, or VDVCC-1 1 μA
BLVDS SERIAL INPUT (RI+, RI-) Differential Input High VTH 9 100 mV
Differential Input Low Threshold VTL -100 -9 mV
0.1V |VID| 0.45V -64 64 Input Current IRI+, IRI-0.45V < |VID| 0.6V -82 82 μA
0.1V |VID| 0.45V, VAVCC = VDVCC = 0V -64 64 Power-Off Input Current IRI+OFF,
IRI-OFF0.45V < |VID| 0.6V, VAVCC = VDVCC = 0V -82 82 μA
Input Resistor 1 RIN1VAVCC = VDVCC = 3.6V or 0V, Figure 2 4 k
Input Resistor 2 RIN2VAVCC = VDVCC = 3.6V or 0V, Figure 2 150 k
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
AC ELECTRICAL CHARACTERISTICS (VAVCC= VDVCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID|= 0.15V to 1.2V, common-mode voltage VCM= |VID/2|
to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC= VDVCC= +3.3V, VCM= 1.1V, |VID|=
0.2V, TA=+25°C.) (Notes 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK) MAX9206 16 45 REFCLK Frequency fRFF
MAX9208 40 60
MHz
REFCLK Frequency Variation RFFV -200 200 ppm
MAX9206 22.222 62.500 REFCLK Period tRFCPMAX9208 16.666 25 ns
REFCLK Duty Cycle RFDC 30 50 70 %
REFCLK Input Transition Time tRFTT 3 6 ns
SWITCHING CHARACTERISTICS MAX9206 22.222 62.500 Recovered Clock (RCLK)
Period (Note 6) tRCPMAX9208 16.666 25 ns
Low-to-High Transition Time tCLH Figure 3 1.5 3 ns
High-to-Low Transition Time tCHL Figure 3 2 3 ns
MAX9206, 45MHz 1.75 x tRCP
+ 2
1.75 x tRCP
+ 3.3
1.75 x tRCP
+ 6.5
Deserializer Delay tDD Figure 4
MAX9208, 60MHz 1.75 x tRCP
+ 1.1
1.75 x tRCP
+ 3.3
1.75 x tRCP
+ 5.6
ns
ROUT_ Data Valid Before RCLK tROSFigure 5 0.4 x tRCP0.5 x tRCP ns
ROUT_ Data Valid After RCLK tROH Figure 5 0.4 x tRCP0.5 x tRCP ns
RCLK Duty Cycle tRDC 43 50 57 %
OUTPUT High-to-High
Impedance Delay tHZR CL = 5pF, Figure 6 8ns
OUTPUT Low-to-High
Impedance Delay tLZR CL = 5pF, Figure 6 8 ns
OUTPUT High-Impedance to
High-State Delay tZHR CL = 5pF, Figure 6 6 ns
OUTPUT High-Impedance to
Low-State Delay tZLRCL = 5pF, Figure 6 6 ns
PLL Lock Time (from PWRDN
Transition High) tDSR1
Sync patterns at input; supply and
REFCLK stable; measured from
PWRDN transition high to LOCK
transition low; Figure 7
(2048 + 42)
x tRFCPns
MAX9206/MAX9208Note 1:Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation.
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground
except VTH, VTL, and VID, which are differential input voltages.
Note 3:DC parameters are production tested at TA= +25°C and guaranteed by design and characterization over operating temper-
ature range.
Note 4:AC parameters guaranteed by design and characterization.
Note 5:CLincludes scope probe and test jig capacitance.
Note 6:tRCPis determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequen-
cy of TCLK must be within ±400ppm of the REFCLK frequency.
AC ELECTRICAL CHARACTERISTICS (continued)(VAVCC= VDVCC= +3.0V to +3.6V, CL= 15pF, differential input voltage |VID|= 0.15V to 1.2V, common-mode voltage VCM= |VID/2|
to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC= VDVCC= +3.3V, VCM= 1.1V, |VID|=
0.2V, TA=+25°C.) (Notes 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PLL Lock Time (from Start of
Sync Patterns) tDSR2
PLL locked to stable REFCLK; supply
stable; static input; measured from
start of sync patterns at input to LOCK
transition low; Figure 8 42 x tRFCPns
LOCK High-Z to High-State
Delay tZHLK Figure 7 30 ns
16MHz 1300 MAX9206 45MHz 720
40MHz 720 Input Jitter Tolerance tJT Figure 9
MAX9208 60MHz 320
ps
10-Bit Bus LVDS Deserializers
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
Pin Description
PIN NAME FUNCTION 1, 12, 13 AGND Analog Ground
2 RCLK_R/F
Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe
ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of
RCLK. REFCLK PLL Reference Clock. LVTTL/LVCMOS level input.
4, 11 AVCC Analog Power Supply. Bypass AVCC with a 0.1μF and a 0.001μF capacitor to AGND. RI+Serial Data Input. Noninverting BLVDS differential input. RI- Serial Data Input. Inverting BLVDS differential input. PWRDN Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
8 REN Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance. LOCK remains active, indicating the status of the serial input. RCLK Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_. LOCK Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
14, 20, DGND Digital Ground
15–19,
24–28
ROUT9–
ROUT0
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low.
21, 23 DVCC Digital Power Supply. Bypass DVCC with a 0.1μF and a 0.001μF capacitor to DGND.
Figure 1. Worst-Case ICCTest Pattern0
END
BIT987654310
START
BIT
END
BIT976543212182
START
BIT
TDD
RCLK_R/F = HIGH
START
BIT
RCLK
ODD
ROUT
EVEN
ROUT
Test Circuits/Timing Diagrams
MAX9206/MAX9208
10-Bit Bus LVDS DeserializersFigure 5. Data Valid Times
tROStROH
RCLK
RCLK_R/F = LOW
RCLK
RCLK_R/F = HIGH
DATA VALID
BEFORE RCLK
DATA VALID
AFTER RCLKROUT_
50%
50%
Figure 6. High-Impedance Test Circuit and Timing
+7V FOR tLZR AND tZLR
OPEN FOR tHZR AND tZHR
450Ω
500Ω
SCOPE
50Ω
REN
ROUT_
RCLK
VOL
VOH
tLZR
tHZR
tZLR1.5V
tZHR
VOL +0.5V
VOH -0.5V
Figure 2. Input Fail-Safe Circuit
VCC
VCC - 0.3VTO DESERIALIZING
CIRCUITRY
RI+
RI-
RIN1
RIN1
RIN2
Figure 3. LVCMOS/LVTTL Output Load and Transition Times
80%80%
20%20%
tCLHtCHL
15pF
LVCMOS/LVTTL
OUTPUT
Figure 4. Input-to-Output Delay
START
BIT
START
BITEND
BIT
START
BITEND
BIT
SYMBOL NSYMBOL N+1
SYMBOL N-1SYMBOL N
tDD
RCLK
ROUT_
RCLK_R/F = HIGH
Test Circuits/Timing Diagrams (continued)
