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MAX9205EAIMAXIM,MAXIMN/a25000avai10-Bit Bus LVDS Serializers


MAX9205EAI ,10-Bit Bus LVDS SerializersApplicationsThe MAX9205/MAX9207 transmit serial data at speeds Wide Reference Clock Input Rangeup ..
MAX9205EAI+ ,10-Bit Bus LVDS SerializersApplicationsMAX9207EAI+ -40°C to +85°C 28 SSOP 40 to 66Cellular Phone Base DSLAMs+Denotes a lead(Pb ..
MAX9205EAI+T ,10-Bit Bus LVDS SerializersELECTRICAL CHARACTERISTICS(V = V = +3.0V to +3.6V, R = 27Ω ±1% or 50Ω ±1%, C = 10pF, T = -40°C to + ..
MAX9206EAI ,10-Bit Bus LVDS DeserializersApplicationsMAX9206EAI -40°C to +85°C 16 to 40 28 SSOPCellular Phone Base DSLAMsMAX9208EAI -40°C to ..
MAX9206EAI+ ,10-Bit Bus LVDS DeserializersELECTRICAL CHARACTERISTICS(V = V = +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.2V, ..
MAX9206EAI+T ,10-Bit Bus LVDS DeserializersApplicationssize.♦ Fast Pseudorandom LockThe MAX9206/MAX9208 receive serial data at450Mbps and 600M ..
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MAX9205EAI
10-Bit Bus LVDS Serializers
General Description
The MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206*/MAX9208*, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PC
board traces or twisted-pair cables. Since the clock is
recovered from the serial data stream, clock-to-data
and data-to-data skew that would be present with a
parallel bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDNis used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Applications
Features
Standalone Serializer (vs. SERDES) Ideal for
Unidirectional Links
Framing Bits for Deserializer Resync Allow Hot
Insertion Without System Interruption
LVDS Serial Output Rated for Point-to-Point and
Bus Applications
Wide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)
Low 140ps (pk-pk) Deterministic Jitter (MAX9207)Low 34mA Supply Current (MAX9205)10-Bit Parallel LVCMOS/LVTTL InterfaceUp to 660Mbps Payload Data Rate (MAX9207)Programmable Active Edge on Input LatchPin-Compatible Upgrades to DS92LV1021 and
DS92LV1023
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Ordering Information

19-2029; Rev 0; 5/01
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application Circuit

Cellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
*Future product–contact factory for availability.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA=
+25°C, unless otherwise noted.) (Notes 1, 2, 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND.........................................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDNto GND......................................-0.3V to (VCC+ 0.3V)
OUT+, OUT- to GND.............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C)..........762mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Lead Temperature (soldering, 10s).................................+300°C
ESD Protection (Human Body Model, OUT+, OUT-)...........±8kV
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA=
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Typical Operating Characteristics

(VCC= +3.3V, RL= 27Ω, CL = 10pF, TA = +25°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA=
+25°C, unless otherwise noted.) (Notes 2, 4)
except VOD, ∆VOD, and VOS.
Note 2:
CLincludes scope probe and test jig capacitance.
Note 3:
Parameters 100% tested at TA = +25°C. Limits over operating temperature range guaranteed by design and characterization.
Note 4:
AC parameters are guaranteed by design and characterization.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Pin Description
Detailed Description

The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PC board traces at
160Mbps to 660Mbps. The interface may be double-
terminated point-to-point or a heavily loaded multipoint
bus. The characteristic impedance of the media and
connected devices can range from 100Ωfor a point-to-
point interface to 54Ωfor a heavily loaded multipoint
bus. A double-terminated point-to-point interface uses
a 100Ω-termination resistor at each end of the inter-
face, resulting in a load of 50Ω. A heavily loaded multi-
point bus requires a termination as low as 54Ωat each
end of the bus, resulting in a termination load of 27Ω.
The serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
MAX9205/MAX9207
Initialization Mode

When VCCis applied, the outputs are held in high
impedance and internal circuitry is disabled by on-chip
power-on-reset circuitry. When VCCreaches 2.35V, the
PLL starts to lock to a local reference clock (16MHz to
40MHz for MAX9205 and 40MHz to 66MHz for
MAX9207). The reference clock, TCLK, is provided by
the system. A serializer locks within 2049 cycles of
TCLK. Once locked, a serializer is ready to send data
or SYNC patterns depending on the levels of SYNC 1
and SYNC 2.
Synchronization Mode

To rapidly synchronize with a deserializer, SYNC pat-
terns can be sent. A SYNC pattern is six consecutive
ones followed by six consecutive zeros repeating every
TCLK period. When one or both SYNC inputs are
asserted high for at least six cycles of TCLK, the serial-
izer will initiate the transmission of 1024 SYNC patterns.
The serializer will continue to send SYNC patterns if
either of the SYNC input pins remains high. Toggling
one SYNC input with the other SYNC input low before
1024 SYNC patterns are output does not interrupt the
output of the 1024 SYNC patterns.
Data Transmission Mode

After initialization, both SYNC input pins must be set
low by users or through a control signal from the dese-
rializer before data transmission begins. Provided that
SYNC inputs are low, input data at IN0–9 are clocked
into the serializer by the TCLK input. Setting TCLK_R/F
high selects the rising edge of TCLK for data strobe
and low selects the falling edge. If either of the SYNC
inputs goes high for six TCLK cycles at any time during
data transmission, the data at IN0–9 are ignored and
SYNC patterns are sent for at least 1024 TCLK cycles.
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
Power-Down

Power-down mode is entered when the PWRDNpin is
driven low. In power-down mode, the PLL of the serial-
izer is stopped and the outputs (OUT+ and OUT-) are
in high impedance, disabling drive current and also
reducing supply current. When PWRDNis driven high,
the serializer must reinitialize and resynchronize before
data can be transferred.
High-Impedance State

The serializer output pins (OUT+ and OUT-) are held in
high impedance when VCCis first applied and while the
PLL is locking to the local reference clock. Setting EN
or PWRDNlow puts the device in high impedance.
After initialization, EN functions asynchronously. For
example, the serializer output can be put into high
impedance while SYNC patterns are being sent without
affecting the internal timing of the SYNC pattern gener-
ation. However, if the serializer goes into high imped-
ance, a deserializer loses PLL lock and needs to
resynchronize before data transfer can resume.
10-Bit Bus LVDS Serializers
Table 1. Input /Output Function Table
Applications Information
Power-Supply Bypassing

Bypass AVCCwith high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AVCC. Bypass DVCCwith high-fre-
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DVCC.
Differential Traces and Termination

Output trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100Ωtermination, the
output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90°turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers

Figure 1. Output Voltage Definitions
Figure 2. Worst-Case ICCTest Pattern
Figure 3. Input Clock Transition Time Requirement
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