MAX9205EAI+T ,10-Bit Bus LVDS SerializersELECTRICAL CHARACTERISTICS(V = V = +3.0V to +3.6V, R = 27Ω ±1% or 50Ω ±1%, C = 10pF, T = -40°C to + ..
MAX9206EAI ,10-Bit Bus LVDS DeserializersApplicationsMAX9206EAI -40°C to +85°C 16 to 40 28 SSOPCellular Phone Base DSLAMsMAX9208EAI -40°C to ..
MAX9206EAI+ ,10-Bit Bus LVDS DeserializersELECTRICAL CHARACTERISTICS(V = V = +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.2V, ..
MAX9206EAI+T ,10-Bit Bus LVDS DeserializersApplicationssize.♦ Fast Pseudorandom LockThe MAX9206/MAX9208 receive serial data at450Mbps and 600M ..
MAX9207EAI+ ,10-Bit Bus LVDS SerializersFeaturesThe MAX9205/MAX9207 serializers transform 10-bit-♦ Standalone Serializer (vs. SERDES) Ideal ..
MAX9207EAI+T ,10-Bit Bus LVDS SerializersApplicationsThe MAX9205/MAX9207 transmit serial data at speeds♦ Wide Reference Clock Input Rangeup ..
MB88347 ,R-2R TYPE 8-BIT D/A CONVERTER WITH OPERATIONAL AMPLIFIER OUTPUT BUFFERSFUJITSU SEMICONDUCTORDS04-13506-1EDATA SHEETLINEAR ICR-2R TYPE 8-BIT D/A CONVERTER WITHOPERATIONAL ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MB88347L ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FUJITSU SEMICONDUCTORDS04-13512-2EDATA SHEETLinear IC converterCMOSD/A Converter for Digital Tuning ..
MB88347LPFV ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FUJITSU SEMICONDUCTORDS04-13512-2EDATA SHEETLinear IC converterCMOSD/A Converter for Digital Tuning ..
MB88347LPFV ,D/A Converter for Digital Tuning (8-channel, 8-bit, on-chip OP amp, low-voltage)FEATURES• Ultra-low power consumption (0.5 mW/ch: typical)• Low voltage operation (VCC = 2.7 to 3. ..
MAX9205EAI+-MAX9205EAI+T-MAX9207EAI+-MAX9207EAI+T
10-Bit Bus LVDS Serializers
MAX9205/MAX9207
10-Bit Bus LVDS SerializersEVALUATION KIT AVAILABLE
General DescriptionThe MAX9205/MAX9207 serializers transform 10-bit-
wide parallel LVCMOS/LVTTL data into a serial high-
speed bus low-voltage differential signaling (LVDS)
data stream. The serializers typically pair with deserial-
izers like the MAX9206/MAX9208, which receive the
serial output and transform it back to 10-bit-wide paral-
lel data.
The MAX9205/MAX9207 transmit serial data at speeds
up to 400Mbps and 660Mbps, respectively, over PCB
traces or twisted-pair cables. Since the clock is recov-
ered from the serial data stream, clock-to-data and
data-to-data skew that would be present with a parallel
bus are eliminated.
The serializers require no external components and few
control signals. The input data strobe edge is selected
by TCLK_R/F. PWRDNis used to save power when the
devices are not in use. Upon power-up, a synchroniza-
tion mode is activated, which is controlled by two SYNC
inputs, SYNC1 and SYNC2.
The MAX9205 can lock to a 16MHz to 40MHz system
clock, while the MAX9207 can lock to a 40MHz to
66MHz system clock. The serializer output is held in
high impedance until the device is fully locked to the
local system clock, or when the device is in power-
down mode.
Both the devices operate from a single +3.3V supply,
are specified for operation from -40°C to +85°C, and
are available in 28-pin SSOP packages.
Applications
FeaturesStandalone Serializer (vs. SERDES) Ideal for
Unidirectional LinksFraming Bits for Deserializer Resync Allow Hot
Insertion Without System InterruptionLVDS Serial Output Rated for Point-to-Point and
Bus ApplicationsWide Reference Clock Input Range
16MHz to 40MHz (MAX9205)
40MHz to 66MHz (MAX9207)Low 140ps (pk-pk) Deterministic Jitter (MAX9207)Low 34mA Supply Current (MAX9205)10-Bit Parallel LVCMOS/LVTTL InterfaceUp to 660Mbps Payload Data Rate (MAX9207)Programmable Active Edge on Input LatchPin-Compatible Upgrades to DS92LV1021 and
DS92LV1023PCB OR
TWISTED PAIRTCLK
PLLPLLENEN
PWRDN
INPUT LATCH
PARALLEL-TO-SERIAL
OUTPUT LATCH
SERIAL-TO-PARALLEL
TIMING AND
CONTROL
TIMING AND
CONTROL
CLOCK
RECOVERY
RCLK
LOCK
SYNC 1
SYNC 2
OUT+
OUT-
IN+
IN-
100Ω100Ω
TCLK_R/F
RCLK_R/F
REFCLK
OUT_IN_10
BUS
LVDS
MAX9205
MAX9207
MAX9206
MAX9208
Ordering Information
PARTTEMP
RANGE
PIN-
PACKAGE
REF CLOCK
RANGE
(MHz)
MAX9205EAI+-40°C to +85°C28 SSOP16 to 40AX 9205E AI/V + -40°C to +85°C28 SSOP16 to 40
MAX9207EAI+-40°C to +85°C28 SSOP40 to 66
Pin Configuration and Functional Diagram appear at end of
data sheet.
Typical Application CircuitCellular Phone Base
Stations
Add Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches and
Routers
Backplane Interconnect
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VAVCC= VDVCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC=
VDVCC= +3.3V and TA= +25°C, unless otherwise noted.) (Notes 2, 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC to GND..........................……………-0.3V to +4.0V
IN_, SYNC1, SYNC2, EN, TCLK_R/F, TCLK,
PWRDNto GND......................................-0.3V to (VCC+ 0.3V)
OUT+, OUT- to GND.............................................-0.3V to +4.0V
Output Short-Circuit Duration.....................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C)..........762mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
ESD Protection (Human Body Model, OUT+, OUT-)...........±8kV
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, SYNC1, SYNC2, TCLK, TCLK_R/F, PWRDN)High-Level Input VoltageVIH2.0VCCV
Low-Level Input VoltageVILGND0.8V
Input CurrentIINVIN_ = 0V or V_VCC-20+20µA
BUS LVDS OUTPUTS (OUT+, OUT-)RL = 27Ω200286400mVDifferential Output VoltageVODFigure 1RL = 50Ω250460600mV
Change in VOD Between
Complementary Output StatesΔVODFigure 1135mV
Output Offset VoltageVOSFigure 10.91.151.3V
Change in VOS Between
Complementary Output StatesΔVOSFigure 1335mV
Output Short-Circuit CurrentIOSVOUT+ or VOUT- = 0V,
IN0 to IN9 = PWRDN = EN = high-13-15mA
Output High-Impedance CurrentIOZVPWRDN or VEN = 0.8V,
VOUT+ or VOUT- = 0V or V_VCC-10+10µA
Power-Off Output CurrentIOXV_VCC = 0V, VOUT+ or VOUT- = 0V or 3.6V-10+10µA
POWER SUPPLY16MHz2335MAX920540MHz3445
40MHz3250Supply CurrentICC
RL = 27_ or 50_
worst-case pattern
(Figures 2, 4)MAX920766MHz4560
Power-Down Supply CurrentICCXPWRDN = low8mA
Note 1:Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)SSOP
Junction-to-Ambient Thermal Resistance (θJA)...............68°C/W
Junction-to-Case Thermal Resistance (θJC)......................25°C/W
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
AC ELECTRICAL CHARACTERISTICS(VAVCC= VDVCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC=
VDVCC= +3.3V and TA= +25°C, unless otherwise noted.) (Notes 3, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS MAX9205 16 40 MHz TCLK Center Frequency fTCCFMAX9207 40 66 MHz
TCLK Frequency Variation TCFV -200 200 ppm
MAX9205 25 62.5 TCLK Period tTCPMAX9207 15.15 25 ns
TCLK Duty Cycle TCDC 40 60 %
TCLK Input Transition Time tCLKT Figure 3 3 6 ns
TCLK Input Jitter tJIT 150 ps
(RMS)
SWITCHING CHARACTERISTICS RL = 27150 300 400 Low-to-High Transition Time tLHT Figure 4
RL = 50150 350 500
ps
RL = 27150 300 400 High-to-Low Transition Time tHLT Figure 4 RL = 50150 350 500 ps
IN_ Setup to TCLK tS Figure 5 1 ns
IN_ Hold from TCLK tH Figure 5 3 ns
OUTPUT High State to High-
Impedance Delay tHZ Figures 6, 7 4.5 10 ns
OUTPUT Low State to High-
Impedance Delay tLZ Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
High-State Delay tZH Figures 6, 7 4.5 10 ns
OUTPUT High Impedance to
Low-State Delay tZL Figures 6, 7 4.5 10 ns
SYNC Pulse Width tSPW 6 x tTCP ns
PLL Lock Time tPL Figure 7 2048 x
tTCP
2049 x
tTCPns
Bus LVDS Bit Width tBIT tTCP/12 ns
Serializer Delay tSD Figure 8 tTCP/ 6 (tTCP/6)
+ 5 ns
Typical Operating Characteristics(VAVCC= VDVCC= +3.3V, RL= 27Ω, CL = 10pF, TA = +25°C, unless otherwise noted.)
MAX9205/MAX9207
10-Bit Bus LVDS SerializersWORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TCLK = 40MHz
MAX9205
WORST-CASE PATTERN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9205 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TCLK = 40MHz
MAX9205
AC ELECTRICAL CHARACTERISTICS (continued)(VAVCC= VDVCC= +3.0V to +3.6V, RL= 27Ω±1% or 50Ω±1%, CL= 10pF, TA= -40°C to +85°C. Typical values are at VAVCC=
VDVCC= +3.3V and TA= +25°C, unless otherwise noted.) (Notes 3, 5)
Note 2:Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VOD, ∆VOD, and VOS.
Note 3:CLincludes scope probe and test jig capacitance.
Note 4:Parameters 100% tested at TA = +25°C. Limits over operating temperature range guaranteed by design and characterization.
Note 5:AC parameters are guaranteed by design and characterization.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 16MHz 200 MAX9205 40MHz 140
40MHz 140 Deterministic Jitter (Figure 9) tDJIT
MAX9207 66MHz 140
ps
(pk-pk)
16MHz 13 MAX9205 40MHz 9
40MHz 9 Random Jitter (Figure 10) tRJIT
MAX9207 66MHz 6
ps
(RMS)
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Pin Description
PINNAMEFUNCTION1, 2SYNC 1,
SYNC 2
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
3–12IN0–IN9LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.TCLK_R/FLVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.TCLK
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
15, 16DGNDDigital Circuit Ground. Connect to ground plane.
17, 26AVCCAnalog Circuit Power Supply (Includes PLL). Bypass AVCC to ground with a 0.1µF capacitor and a
0.001µF capacitor. Place the 0.001µF capacitor closest to AVCC.
18, 20,
23, 25AGNDAnalog Circuit Ground. Connect to ground plane.ENLVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.OUT-Inverting Bus LVDS Differential OutputOUT+Noninverting Bus LVDS Differential OutputPWRDNLVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
27, 28DVCCDigital Circuit Power Supply. Bypass DVCC to ground with a 0.1µF capacitor and a 0.001µF
capacitor. Place the 0.001µF capacitor closest to DVCC.
Detailed DescriptionThe MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PCB traces at 160Mbps
to 660Mbps. The interface may be double-terminated
point-to-point or a heavily loaded multipoint bus. The
characteristic impedance of the media and connected
devices can range from 100Ωfor a point-to-point inter-
face to 54Ωfor a heavily loaded multipoint bus. A dou-
ble-terminated point-to-point interface uses a
100Ω-termination resistor at each end of the interface,
resulting in a load of 50Ω. A heavily loaded multipoint
bus requires a termination as low as 54Ωat each end
of the bus, resulting in a termination load of 27Ω. The
serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Initialization ModeWhen VCCis applied, the outputs are held in high
impedance and internal circuitry is disabled by on-chip
power-on-reset circuitry. When the supply voltage
reaches 2.35V, the PLL starts to lock to a local refer-
ence clock (16MHz to 40MHz for MAX9205 and 40MHz
to 66MHz for MAX9207). The reference clock, TCLK, is
provided by the system. A serializer locks within 2049
cycles of TCLK. Once locked, a serializer is ready to
send data or SYNC patterns depending on the levels of
SYNC 1 and SYNC 2.
Synchronization ModeTo rapidly synchronize with a deserializer, SYNC pat-
terns can be sent. A SYNC pattern is six consecutive
ones followed by six consecutive zeros repeating every
TCLK period. When one or both SYNC inputs are
asserted high for at least six cycles of TCLK, the serial-
izer will initiate the transmission of 1024 SYNC patterns.
The serializer will continue to send SYNC patterns if
either of the SYNC input pins remains high. Toggling
one SYNC input with the other SYNC input low before
1024 SYNC patterns are output does not interrupt the
output of the 1024 SYNC patterns.
Data Transmission ModeAfter initialization, both SYNC input pins must be set
low by users or through a control signal from the dese-
rializer before data transmission begins. Provided that
SYNC inputs are low, input data at IN0–9 are clocked
into the serializer by the TCLK input. Setting TCLK_R/F
high selects the rising edge of TCLK for data strobe
and low selects the falling edge. If either of the SYNC
inputs goes high for six TCLK cycles at any time during
data transmission, the data at IN0–9 are ignored and
SYNC patterns are sent for at least 1024 TCLK cycles.
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
Power-DownPower-down mode is entered when the PWRDNpin is
driven low. In power-down mode, the PLL of the serial-
izer is stopped and the outputs (OUT+ and OUT-) are
in high impedance, disabling drive current and also
reducing supply current. When PWRDNis driven high,
the serializer must reinitialize and resynchronize before
data can be transferred. On power-up, in order for the
MAX9205/MAX9207 to initialize correctly, PWRDNshould
remain below 0.7V until PCLK is stable and all power sup-
plies are within specification.
High-Impedance StateThe serializer output pins (OUT+ and OUT-) are held in
high impedance when the supply voltage is first
applied and while the PLL is locking to the local refer-
ence clock. Setting EN or PWRDNlow puts the device
in high impedance. After initialization, EN functions
asynchronously. For example, the serializer output can
be put into high impedance while SYNC patterns are
being sent without affecting the internal timing of the
SYNC pattern generation. However, if the serializer
goes into high impedance, a deserializer loses PLL
lock and needs to resynchronize before data transfer
can resume.
Table 1. Input /Output Function Table
INPUTSOUTPUTSPWRDN
SYNC 1SYNC 2OUT+, OUT-When either or both SYNC 1
and SYNC 2 are held high for
at least six TCLK cycles
Synchronization Mode. SYNC patterns of six 1s and six 0s are
transmitted every TCLK cycle for at least 1024 TCLK cycles.
Data at IN0–9 are ignored.LLData Transmission Mode. IN0–9 and 2 frame bits are
transmitted every TCLK cycle.XXXX
Output in high-impedance.
X = Don’t care.
MAX9205/MAX9207
10-Bit Bus LVDS Serializers
Applications Information
Power-Supply BypassingBypass AVCC with high-frequency surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to AVCC. Bypass DVCC with high-fre-
quency surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smaller valued capacitor closest to DVCC.
Differential Traces and TerminationOutput trace characteristics affect the performance of
the MAX9205/MAX9207. Use controlled-impedance
media and terminate at both ends of the transmission
line in the media's characteristic impedance.
Termination with a single resistor at the end of a point-
to-point link typically provides acceptable performance.
However, the MAX9205/MAX9207 output levels are
specified for double-terminated point-to-point and mul-
tipoint applications. With a single 100Ωtermination, the
output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90°turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
OUT+
OUT-
VODVOS
Figure 1. Output Voltage Definitions
TCLK
ODD IN_
EVEN IN_
TCLK_R/F = LOW
Figure 2. Worst-Case ICCTest Pattern
TCLK
tCLKT
10%
90%90%
10%
tCLKT
Figure 3. Input Clock Transition Time Requirement
