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MAX9181EXT-T |MAX9181EXTTMAXIMN/a1492avaiLow-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package


MAX9181EXT-T ,Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 PackageApplicationsOrdering InformationDigital Cross-ConnectsTO PPI N - PART TEMP RANGEPAC K A G EM ARK ..
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MAX9181EXT-T
Low-Jitter, Low-Noise LVPECL-to-LVDS Level Translator in an SC70 Package
General Description
The MAX9181 is an LVPECL-to-LVDS level translator
that accepts a single LVPECL input and translates it to
a single LVDS output. It is ideal for interfacing between
LVPECL and LVDS interfaces in systems that require
minimum jitter, noise, power, and space.
Ultra-low, 23psP-Padded deterministic jitter and
0.6psRMSadded random jitter ensure reliable commu-
nication in high-speed links that are highly sensitive to
timing errors, especially those incorporating clock-and-
data recovery, PLLs, serializers, or deserializers. The
MAX9181’s switching performance guarantees a
400Mbps data rate, but minimizes radiated noise by
guaranteeing 0.5ns minimum output transition time.
The MAX9181 operates from a single 3.3V supply and
consumes only 10mA supply current over a -40°C to
+85°C temperature range. It is available in a tiny 6-pin
SC70 package (half the size of a SOT23). Refer to the
MAX9180 data sheet for a low-jitter, low-noise LVDS
repeater in an SC70 package.
Applications

Digital Cross-Connects
Add/Drop Muxes
Network Switches/Routers
Cellular Phone Base Stations
DSLAMs
Multidrop Buses
Features
Tiny SC70 PackageUltra-Low Jitter
23psP-PAdded Deterministic Jitter23 - 1 PRBS)
0.6psRMSAdded Random Jitter
0.5ns (min) Transition Time Minimizes Radiated
Noise
400Mbps Guaranteed Data RateLow 10mA Supply CurrentConforms to ANSI/EIA/TIA-644 LVDS StandardHigh-Impedance Inputs and Outputs in
Power-Down Mode
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Levelranslator in an SC70 Package

GND
IN+IN-OUT+
5VCC
OUT-
MAX9181
SC70

TOP VIEW
Pin Configuration

19-2415; Rev 1; 2/04
Ordering Information
PART TEMP RANGE PIN -
PA C K A G E
TOPM ARK
MAX9181EXT-T-40°C to +85°C6 SC70-6ABI
LVPECL
DRIVER
3.3V
IN+
IN-
OUT+
OUT-
VCC
LVDS
SIGNALS
GND
MAX9181
Typical Operating Circuit
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT+, OUT- to GND.............................................-0.3V to +4.0V
Short-Circuit Duration (OUT+, OUT-).........................Continuous
Continuous Power Dissipation (TA= +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C)..............245mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
ESD Protection
Human Body Model, IN+, IN-, OUT+, OUT-....................±8kV
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, RL= 100Ω±1%, |VID|= 0.05V to VCC, VCM= |VID/ 2|to VCC- |VID/ 2|, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC= 3.3V, TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T S
LVPECL INPUT

Differential Input High ThresholdVTH750mV
Differential Input Low ThresholdVTL-50-7mV
Input ResistorRINFigure 13601328kΩ
IN+ = 3.6V, IN- = 0V-10+2.7+10Input CurrentIIN+, IIN-IN+ = 0V, IN- = 3.6V-10+2.7+10µA
IN+ = 3.6V, IN- = 0V-10+2.7+10Power-Off Input CurrentIIN+, IIN-VCC = 0V,
Figure 1IN+ = 0V, IN- = 3.6V-10+2.7+10µA
LVDS OUTPUT

Differential Output VoltageVODFigure 2250360450mV
Differential Output VoltageΔVODFigure 20.00825mV
Offset (Common-Mode) VoltageVOSFigure 21.1251.251.375V
Change in VOS for
Complementary Output StatesΔVOSFigure 20.00525mV
Output High VoltageVOH1.441.6V
Output Low VoltageVOL0.91.08V
Differential Output VoltageVOD+IN+, IN- open+250+360+450mVU T+ = 3.6V , other outp ut op en-10+0.02+10Power-Off Output Leakage
CurrentIOOFFVCC = 0VO U T- = 3.6V , other outp ut op en-10+0.02+10µA
Differential Output ResistanceRODIFFVCC = 3.6V or 0V100260400Ω
VID = 50mV, OUT+ = GND-5-15Output Short CurrentISCVID = -50mV, OUT- = GND-5-15mA
POWER SUPPLY

Supply CurrentICC1015mA
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Levelranslator in an SC70 Package
Note 1:
All devices are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and characterization.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VOD, and ∆VOD.
Note 3:
Guaranteed by design and characterization.
Note 4:
Signal generator output (unless otherwise noted): frequency = 200MHz, 50% duty cycle, RO= 50Ω, tR= 1.5ns, and tF=
1.5ns (0% to 100%).
Note 5:
CLincludes scope probe and test jig capacitance.
Note 6:
Signal generator output for tDJ: VOD= 150mV, VOS= 1.2V, tDJincludes pulse (duty cycle) skew.
Note 7:
Signal generator output for tRJ: VOD= 150mV, VOS= 1.2V.
Note 8:
tSKPP1is the magnitude difference of any differential propagation delays between devices operating over rated conditions
at the same supply voltage, input common-mode voltage, and ambient temperature.
Note 9:
tSKPP2is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
Note 10:
Device meets VODDC specifications and AC specifications while operating at fMAX.
Note 11:
Jitter added to the input signal.
AC ELECTRICAL CHARACTERISTICS

(VCC= 3.0V to 3.6V, RL= 100Ω±1%, CL= 10pF, |VID|= 0.15V to VCC, VCM= |VID/ 2|to VCC- |VID/ 2|, TA= -40°C to +85°C, unless
otherwise noted. Typical values are at VCC= 3.3V, TA= +25°C.) (Notes 3, 4, 5) (Figures 3, 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T

Differential Propagation Delay High
to LowtPHLD1.32.02.8ns
Differential Propagation Delay Low to
HightPLHD1.32.02.8ns
Added Deterministic JittertDJ400Mbps 223 - 1 PRBS data pattern
(Notes 6, 11)23100psP-P
Added Random JittertRJfIN = 200MHz (Notes 7, 11)0.62.9psRMS
Differential Part-to-Part SkewtSKPP1(Note 8)0.160.6ns
Differential Part-to-Part SkewtSKPP2(Note 9)1.5ns
Switching Supply CurrentICCSW12.218mA
Rise TimetTLH0.50.671.0ns
Fall TimetTHL0.50.661.0ns
Input FrequencyfMAX(Note 10)200MHz
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
100501502002512575175225250
SUPPLY CURRENT
vs. INPUT FREQUENCY

MAX9181 toc01
INPUT FREQUENCY (MHz)
SUPPLY CURRRENT (mA)
SWITCHING SUPPLY CURRENT
vs. TEMPERATURE
MAX9181 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9181 toc03
SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT (mA)
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
MAX9181 toc04
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
MAX9181 toc05
SUPPLY VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
MAX9181 toc06
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
MAX9181 toc07
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY (ns)
tPHLD
tPLHD
TRANSITION TIME
vs. SUPPLY VOLTAGE
MAX9181 toc08
SUPPLY VOLTAGE (V)
TRANSITION TIME (ps)
tTHL
tTLH
Typical Operating Characteristics

(VCC= 3.3V, RL= 100Ω±1%, CL= 10pF, |VID|= 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, RO= 50Ω, tR= 1.5ns, and tF= 1.5ns (0% to 100%), unless otherwise noted.)
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other com-
mon communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9181 is a 400Mbps LVDS translator intended
for high-speed, point-to-point, low-power applications.
The MAX9181 accepts differential LVPECL inputs and
produces an LVDS output. The input voltage range
includes signals from GND up to VCC, allowing interop-
eration with 3.3V LVPECL devices.
The MAX9181 provides a high output when the inputs
are open. See Table 1.
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Levelranslator in an SC70 Package

TRANSITION TIME
vs. TEMPERATURE
MAX9181 toc09
TEMPERATURE (°C)
TRANSITION TIME (ps)
tTLH, tTHL
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
MAX9181 toc10
LOAD RESISTOR (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (mV)50100125
Typical Operating Characteristics (continued)

(VCC= 3.3V, RL= 100Ω±1%, CL= 10pF, |VID|= 0.2V, VCM= 1.2V, TA= +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, RO= 50Ω, tR= 1.5ns, and tF= 1.5ns (0% to 100%), unless otherwise noted.)
Pin Description
PINNAMEFUNCTION
OUT-Inverting LVDS OutputGNDGroundIN-Inverting LVPECL-Compatible InputIN+Noninverting LVPECL-Compatible
Input
5VCCPower Supply. Bypass VCC to GND
with a 0.01µF ceramic capacitor.OUT+Noninverting LVDS Output
INPUT, VIDOUTPUT, VOD
50mVHigh -50mVLow
50mV > VID > -50mVIndeterminate
OpenHigh
Note:
VID= (IN+ - IN-), VOD= (OUT+ - OUT-)
High = 450mV ≥VOD≥250mV
Low = -250mV ≥VOD≥-450mV
Table 1. Function Table (Figure 2)
MAX9181
Applications Information
Supply Bypassing

Bypass VCCwith a high-frequency surface-mount
ceramic 0.01µF capacitor as close to the device as
possible.
Differential Traces

Input and output trace characteristics affect the perfor-
mance of the MAX9181. Use controlled-impedance dif-
ferential traces. Ensure that noise couples as common
mode by running the traces within a differential pair
close together.
Maintain the distance within a differential pair to avoid
discontinuities in differential impedance. Avoid 90°
turns and minimize the number of vias to further prevent
impedance discontinuities.
Cables and Connectors

The LVDS standards define signal levels for intercon-
nect with a differential characteristic impedance and
termination of 100Ω. Interconnects with a characteristic
impedance and termination of 90Ωto 132Ωimpedance
are allowed, but produce different signal levels (see
Termination).
LVPECL signals are typically specified for 50Ωsingle-
ended characteristic impedance interconnect terminat-
ed through 50Ωto VCC- 2V.
Use cables and connectors that have matched differen-
tial impedance to minimize impedance discontinuities.
Termination

For point-to-point LVDS links, the termination resistor
should be located at the LVDS receiver input and
match the differential characteristic impedance of the
transmission line.
Each line of a differential LVPECL link should be termi-
nated through 50Ωto VCC- 2V or be replaced by the
Thevinin equivalent.
The LVDS output voltage level depends upon the differ-
ential characteristic impedance of the interconnect and
the value of the termination resistance. The MAX9181 is
guaranteed to produce LVDS output levels into 100Ω.
With the typical 3.6mA output current, the MAX9181 pro-
duces an output voltage of 360mV when driving a 100Ω
transmission line terminated with a 100Ωtermination
resistor (3.6mA ✕100Ω= 360mV). For typical output lev-
els with different loads, see the Differential Output
Voltage vs. Load Resistor curve in the Typical Operating
Characterics.
Chip Information

TRANSISTOR COUNT: 401
PROCESS: CMOS
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
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