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MAX9110ESAMAXIMN/a6avaiSingle/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
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MAX9112ESAMAXIMN/a82avaiSingle/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23


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MAX9110ESA-MAX9112EKA-T-MAX9112ESA
Single/Dual LVDS Line Drivers with Ultra-Low Pulse Skew in SOT23
General Description
The MAX9110/MAX9112 single/dual low-voltage differ-
ential signaling (LVDS) transmitters are designed for
high-speed applications requiring minimum power con-
sumption, space, and noise. Both devices support
switching rates exceeding 500Mbps while operating
from a single +3.3V supply, and feature ultra-low 250ps
(max) pulse skew required for high-resolution imaging
applications, such as laser printers and digital copiers.
The MAX9110 is a single LVDS transmitter, and the
MAX9112 is a dual LVDS transmitter.
Both devices conform to the EIA/TIA-644 LVDS standard.
They accept LVTTL/CMOS inputs and translate them to
low-voltage (350mV) differential outputs, minimizing elec-
tromagnetic interference (EMI) and power dissipation.
These devices use a current-steering output stage, mini-
mizing power consumption, even at high data rates. The
MAX9110/MAX9112 are available in space-saving 8-pin
SOT23 and SO packages. Refer to the MAX9111/
MAX9113 data sheet for single/dual LVDS line receivers.
________________________Applications
Features
Low 250ps (max) Pulse Skew for High-Resolution
Imaging and High-Speed Interconnect
Space-Saving 8-Pin SOT23 and SO PackagesPin-Compatible Upgrades to DS90LV017/017A
and DS90LV027/027A (SO Packages)
Guaranteed 500Mbps Data RateLow 22mW Power Dissipation at 3.3V
(31mW for MAX9112)
Conform to EIA/TIA-644 StandardSingle +3.3V SupplyFlow-Through Pinout Simplifies PC Board LayoutDriver Outputs High Impedance when Powered Off
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
Pin Configurations/Functional Diagrams/Truth Table

19-1771; Rev 0; 9/00
Ordering Information

Laser Printers
Digital Copiers
Cellular Phone Base
Stations
Telecom Switching
Equipment
Network Switches/Routers
LCD Displays
Backplane Interconnect
Clock Distribution
Typical Operating Circuit appears at end of data sheet.
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA=
AC CHARACTERISTICS

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCCto GND)..................................-0.3V to +4V
Input Voltage (VDIN_ to GND).....................-0.3V to (VCC+ 0.3V)
Output Voltage (VDO_+, VDO_- to GND or VCC)...-0.3V to +3.9V
Output Short-Circuit Duration
(DO_+, DO_- to VCCor GND)................................Continuous
ESD Protection (Human Body Model, DO_+, DO_-)..........±11kV
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 7.52mW/°C above +70°C)...........602mW
8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering,10s)..................................+300°C
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
AC CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, RL= 100Ω±1%, CL= 5pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V,= +25°C.) (Notes 3, 4, 5; Figures 2, 3)
Note 1:
Maximum and minimum limits over temperature are guaranteed by design. Devices are production tested at TA= +25°C.
Note 2:
By definition, current into the device is positive and current out of the device is negative. Voltages are referred to device
ground except VOD.
Note 3:
ACparameters are guaranteed by design and characterization.
Note 4:
CLincludes probe and fixture capacitance.
Note 5:
Signal generator conditions for dynamic tests: VOL= 0, VOH= 3V, f = 20MHz, 50% duty cycle, RO= 50Ω, tR≤1ns, and tF≤
1ns (0 to 100%).
Note 6:
tSKD1is the magnitude difference of differential propagation delays in a channel; tSKD1 = |tPHLD - tPLHD |.
Note 7:
tSKD2is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on the
same device (MAX9112).
Note 8:
tSKD3is the magnitude difference of any differential propagation delays between devices at the same VCCand within 5°C
of each other.
Note 9:
tSKD4is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 10:fMAX
signal generator conditions: VOL = 0, VOH= +3V, frequency = 250MHz, tR≤1ns, tF≤1ns (0 to 100%) 50% duty cycle.
Transmitter output criteria: duty cycle = 45% to 55%, VOD≥250mV.
Typical Operating Characteristics

(VCC= +3.3V, RL = 100Ω, CL = 5pF, VIH= +3V, VIL= GND, fIN= 20MHz, TA= +25°C, unless otherwise noted.) (Figures 2, 3)
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
Typical Operating Characteristics (continued)
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23

MAX9110 toc12
LOAD RESISTANCE (Ω)
OUTPUT HIGH VOLTAGE (V)
OUTPUT HIGH VOLTAGE
vs. LOAD RESISTANCE

MAX9110 toc13
LOAD RESISTANCE (Ω)
OUTPUT LOW VOLTAGE (V)
OUTPUT LOW VOLTAGE
vs. LOAD RESISTANCE
Typical Operating Characteristics (continued)

(VCC= +3.3V, RL = 100Ω, CL = 5pF, VIH= +3V, VIL= GND, fIN= 20MHz, TA= +25°C, unless otherwise noted.) (Figures 2, 3)
Pin Description
Detailed Description

The MAX9110/MAX9112 single/dual LVDS transmitters
are intended for high-speed, point-to-point, low-power
applications. These devices accept CMOS/LVTTL
inputs with data rates exceeding 500Mbps. The
MAX9110/MAX9112 reduce power consumption and
EMI by translating these signals to a differential voltage
in the 250mV to 450mV range across a 100Ωload while
drawing only 9.4mA of supply current for the dual-
channel MAX9112.
A current-steering approach induces less ground
bounce and no shoot-through current, enhancing noise
margin and system speed performance. The output
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23

stage presents a symmetrical, high-impedance output,
reducing differential reflection and timing distortion. The
driver outputs are short circuit current limited and enter a
high-impedance state when the device is not powered.
LVDS Operation

The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled impedance medium as defined by the EIA/TIA-
644 LVDS standard. The LVDS standard uses a lower
voltage swing than other common communication stan-
dards, achieving higher data rates with reduced power
consumption while reducing EMI emissions and system
susceptibility to noise.
LVDS transmitters such as the MAX9110/MAX9112
convert CMOS/LVTTL signals to low-voltage differential
signals at rates in excess of 500Mbps. The MAX9110/
MAX9112 current-steering architecture requires a resis-
tive load to terminate the signal and complete the trans-
mission loop. Because the device switches the direc-
tion of current flow and not voltage levels, the actual
output voltage swing is determined by the value of the
termination resistor at the input of an LVDS receiver.
Logic states are determined by the direction of current
flow through the termination resistor. With a typical
3.5mA output current, the MAX9110/MAX9112 produce
an output voltage of 350mV when driving a 100Ωload.
The steady-state-voltage peak-to-peak swing is twice
the differential voltage, or 700mV (typ).
Applications Information
Supply Bypassing

Bypass VCCwith high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel, as close to the
device as possible, with the smaller valued capacitor the
closest. For additional supply bypassing, place a 10µF
tantalum or ceramic capacitor at the point where power
enters the circuit board.
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