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MAX8588ETM+ |MAX8588ETMMAXIMN/a2828avaiHigh-Efficiency, Low-IQ PMIC with Dynamic Core for PDAs and Smartphones
MAX8588ETM+T |MAX8588ETMTMAXIMN/a81avaiHigh-Efficiency, Low-IQ PMIC with Dynamic Core for PDAs and Smartphones


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MAX8588ETM+-MAX8588ETM+T
High-Efficiency, Low-IQ PMIC with Dynamic Core for PDAs and Smartphones
General Description
The MAX8588 power-management IC is optimized for
devices using Intel X-Scale™ microprocessors, includ-
ing smartphones, PDAs, internet appliances, and other
portable devices requiring substantial computing and
multimedia capability at low power.
The IC integrates seven high-performance, low-operating-
current power supplies along with supervisory and
management functions. Included are three step-down
DC-DC outputs, three linear regulators, and a seventh
always-on output. DC-DC converters power I/O, memo-
ry, and the CPU core. The I/O supply can be preset to
3.3V or adjusted to other values.The DRAM supply is
preset for 3.3V or 2.5V, or it can be adjusted with exter-
nal resistors. The CPU core supply is serial pro-
grammed for dynamic voltage management and can
supply up to 0.5A. Linear-regulated outputs are provid-
ed for SRAM, PLL, and USIM supplies.
To minimize quiescent current, critical power supplies
have bypass “sleep” LDOs that can be activated when
output current is very low. Other functions include sep-
arate on/off control for all DC-DC converters, low-bat-
tery and dead-battery detection, a reset and power-OK
output, a backup-battery input, and a two-wire serial
interface.
All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre-
quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The core out-
put can be forced into PWM mode at all loads to mini-
mize noise.A 2.6V to 5.5V input voltage range allows
1-cell lithium-ion (Li+), 3-cell NiMH, or a regulated 5V
input. The MAX8588 is available in a tiny 6mm x 6mm,
48-pin thin QFN package.
Applications

PDA, Palmtop, and Wireless Handhelds
Third-Generation Smart Cell Phones
Internet Appliances and Web-Books
Features
Six Regulators in One Package
Step-Down DC-DC for I/O at 1.3A
Step-Down DC-DC for Memory at 0.9A
Step-Down Serial-Programmed DC-DC for CORE
Up to 0.5A
Three LDO Outputs for SRAM, PLL, and USIM
Always-On Output for VCC_BATT
Low Operating Current
60µA in Sleep Mode (Sleep LDOs On)
130µA with DC-DCs On (Core Off)
200µA All Regulators On, No Load
5µA Shutdown Current
Optimized for X-Scale ProcessorsBackup-Battery Input1MHz PWM Switching Allows Small External
Components
Tiny 6mm x 6mm, 48-Pin Thin QFN Package
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones

MAX8588
VCC_IO 3.3V
VCC_MEM 2.5V
VCC_CORE
0.8V TO 1.3V
VCC_USIM
0V, 1.8V, 3.0V
MAIN BATTERY
VCC_PLL 1.3V
VCC_SRAM 1.1V
BACKUP
BATTERY
BKBT
RSO
VCC_BATT
POK
nRESET
nVCC_FAULT
SYS_EN
PWR_EN
ON1-2
ON3-6
nBATT_FAULTDBO
Simplified Diagram

19-3527; Rev 0; 3/05
Pin Configuration appears at end of data sheet.

X-Scale is a trademark of Intel Corp.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE

MAX8588ETM-40°C to +85°C48 Thin QFN (6mm x 6mm)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, IN45, IN6, MR, LBO, DBO, RSO, POK, SCL, SDA,
BKBT, V7, SLP, SRAD, PWM3 to GND...............-0.3V to +6V
REF, CC_, ON_, FB_, DBI, LBI, V1, V2, RAMP, BYP,to GND ...........................................-0.3V to (VIN+ 0.3V)
PV1, PV2, PV3, SLPIN to IN...................................-0.3V to +0.3V
V4, V5 to GND..........................................-0.3V to (VIN45 + 0.3V)
V6 to GND..................................................-0.3V to (VIN6 + 0.3V)
PV1 to PG1............................................................-0.3V to +6.0V
PV2 to PG2............................................................-0.3V to +6.0V
PV3 to PG3............................................................-0.3V to +6.0V
LX1 Continuous Current....................................-1.30A to +1.30A
LX2 Continuous Current........................................-0.9A to +0.9A
LX3 Continuous Current........................................-0.5A to +0.5A
PG1, PG2, PG3 to GND.........................................-0.3V to +0.3V
V1, V2, V4, V5, V6 Output Short-Circuit Duration.......Continuous
Continuous Power Dissipation (TA = +70°C)
6mm x 6mm 48-Pin Thin QFN
(derate 26.3mW/°C above +70°C)...........................2105mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally2.65.5V
IN45, IN6 Supply Voltage Range2.45.5V
VIN rising2.252.402.55IN Undervoltage-Lockout (UVLO)
ThresholdVIN falling2.2002.352.525V
Only V7 on, VIN = 3.0V32
REG1 and REG2 on in switch mode,
REG3 off130
REG1 and REG2 on in sleep mode,
REG3 off60
Quiescent Current
No load (IPV1 +
IPV2 + IPV3 + IIN +
ISLPIN + IIN45 +
IIN6)
All REGs on225
ON1 = 04BKBT Input CurrentON1 = IN0.8µA
REF Output Voltage0 to 10µA load1.23751.251.2625V
SYNCHRONOUS-BUCK PWM REG1

REG1 Voltage AccuracyFB1 = GND, 3.6V ≤ VPV1 ≤ 5.5V, load = 0 to 1300mA3.253.33.35V
FB1 Voltage AccuracyFB1 used with external resistors, 3.6V ≤ VPV1 ≤ 5.5V,
load = 0 to 1300mA1.2311.251.269V
FB1 Input CurrentFB1 used with external resistors100nA
Error-Amplifier TransconductanceReferred to FB87µS
Load = 800mA180280Dropout Voltage (Note 1)Load = 1300mA293450mV
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINTYPMAXUNITS

ILX1 = -180mA0.180.3p-Channel On-ResistanceILX1 = -180mA, VPV1 = 2.6V0.210.35Ω
ILX1 = 180mA0.130.225n-Channel On-ResistanceILX1 = 180mA, VPV1 = 2.6V0.150.25Ω
Current-Sense Transresistance0.5V/A
p-Channel Current-Limit Threshold-1.55-1.80-2.10A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
OUT1 Maximum Output Current2.6V ≤ VPV1 ≤ 5.5V (Note 3)1.3A
LX1 Leakage CurrentVPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V-20+0.1+20µA
SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA2.4632.52.537REG2 Voltage AccuracyFB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA3.253.33.35V
FB2 Voltage AccuracyFB2 used with external resistors, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.2311.251.269V
FB2 Input CurrentFB2 used with external resistors, VFB2 = 1.25V100nA
Error-Amplifier TransconductanceReferred to FB87µS
Dropout VoltageLoad = 900mA (Note 1)243380mV
ILX2 = -180mA0.2250.375p-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.260.425Ω
ILX2 = 180mA0.150.25n-Channel On-ResistanceILX2 = 180mA, VPV2 = 2.6V0.170.275Ω
Current-Sense Transresistance0.7V/A
p-Channel Current-Limit Threshold-1.10-1.275-1.50A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
OUT2 Maximum Output Current2.6V ≤ VPV2 ≤ 5.5V (Note 3)0.9A
LX2 Leakage CurrentVPV2 = 5.5V, LX2 = GND or PV2, VON2 = 0V-10+0.1+10µA
SYNCHRONOUS-BUCK PWM REG3

REG3 Voltage AccuracyREG3 from 0.7V to 1.475V,
2.6V ≤ VPV3 ≤ 5.5VLoad = 0 to 500mA-1.5+1.5%
Error-Amplifier Transconductance68µS
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINTYPMAXUNITS

ILX3 = -180mA0.2250.375p-Channel On-ResistanceILX2 = -180mA, VPV3 = 2.6V0.260.425Ω
ILX3 = 180mA0.150.25n-Channel On-ResistanceILX3 = 180mA, VPV3 = 2.6V0.170.275Ω
Current-Sense Transresistance1.1V/A
p-Channel Current-Limit Threshold-0.60-0.7-0.85A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
OUT3 Maximum Output Current2.6V ≤ VPV3 ≤ 5.5V (Note 3)0.5A
LX3 Leakage CurrentVPV3 = 5.5V, LX3 = GND or PV2, VON3 = 0V-10+0.1+10µA
LDOS V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current35mA
V7 Output Current30mA
REG4 Output VoltageLoad = 0.1mA to 35mA1.2611.31.339V
REG4 NoiseWith 1µF COUT and 0.01µF CBYP15µVRMS
REG5 Output VoltageLoad = 0.1mA to 35mA1.0671.11.133V
IN45, IN6 Input Voltage Range2.45.5V
0V setti ng ( ei ther ON 6 l ow or ser i al p r og r am m ed ) 0
1.8V setting, load = 0.1mA to 35mA1.7461.81.854
2.5V setting, load = 0.1mA to 35mA2.4252.52.575
REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)
3.0V setting, load = 0.1mA to 35mA2.913.03.09
V1 on and in regulationVV1V7 Output VoltageV1 offVBKBTV
V1 and V2 SLEEP Output Voltage
AccuracySet to same output voltage as REG1 and REG2-3.0+3.0%
V1 and V2 SLEEP Dropout VoltageLoad = 20mA75150mV
V6 Dropout Voltage3V m od e, l oad = 30m A, 2.5V m od e, l oad = 30m A110200mV
V7 Switch Voltage DropLoad = 20mA, VBKBT = VV1 = 3.0V100200mV
V4, V5, V6 Output Current Limit 40 90 mA
BKBT Leakage 1 µA
OSCILLATOR

PWM Switching Frequency0.9311.07MHz
SUPERVISORY/MANAGEMENT FUNCTIONS

Rising9294.7597POK Trip Threshold (Note 4)Falling88.590.592.5%
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINTYPMAXUNITS

LBI = IN (for preset)3.513.63.69LBI Threshold (Falling)Hysteresis is 5% (typ)With resistors at LBI0.981.001.02V
DBI = IN (for preset)3.0243.153.276DBI Threshold (Falling)Hysteresis is 5% (typ)With resistors at LBI1.2081.2321.256V
RSO Threshold (Falling)Voltage on REG7, hysteresis is 5% (typ)2.252.412.56V
RSO Deassert Delay6165.570ms
LBI Input Bias Current-50-5nA
DBI Input Bias Current1550nA
Thermal-Shutdown TemperatureTJ rising+160°C
Thermal-Shutdown Hysteresis15°C
LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level2.6V ≤ V7 ≤ 5.5V, sinking 1mA0.4V
LBO, DBO, POK, RSO Output Low
LevelV7 = 1V, sinking 100µA0.4V
LBO, DBO, POK, RSO Output-High
Leakage CurrentPin = 5.5V0.2µA
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level2.6V ≤ VIN ≤ 5.5V1.6V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level2.6V ≤ VIN ≤ 5.5V0.4V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage CurrentPin = GND, 5.5V-1+1µA
SERIAL INTERFACE

Clock Frequency400kHz
Bus Free Time Between START and
STOP1.3µsol d Ti m e Rep eated S TART C ond i ti on0.6µs
CLK Low Period1.3µs
CLK High Period0.6µsetup Ti m e Rep eated S TART C ond i ti on0.6µs
DATA Hold Time0µs
DATA Setup Time100ns
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input
Filter of Both DATA and CLK Signalsns
Setup Time for STOP Condition0.6µs
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINMAXUNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally2.65.5V
IN45, IN6 Supply Voltage Range2.45.5V
VIN rising2.252.55IN Undervoltage-Lockout (UVLO)
ThresholdVIN falling2.2002.525V
SYNCHRONOUS-BUCK PWM REG1

REG1 Voltage AccuracyFB1 = GND, 3.6V ≤ VPV1 ≤ 5.5V, load = 0 to 1300mA3.253.35V
FB1 Voltage AccuracyFB1 used with external resistors, 3.6V ≤ VPV1 ≤ 5.5V,
load = 0 to 1300mA1.2311.269V
FB1 Input CurrentFB1 used with external resistors100nA
Load = 800mA (Note 1)280Dropout VoltageLoad = 1300mA (Note 1)450mV
ILX1 = -180mA0.3p-Channel On-ResistanceILX1 = -180mA, VPV1 = 2.6V0.35Ω
ILX1 = 180mA0.225n-Channel On-ResistanceILX1 = 180mA, VPV1 = 2.6V0.25Ω
p-Channel Current-Limit Threshold-1.55-2.10A
OUT1 Maximum Output Current2.6V ≤ VPV1 ≤ 5.5V (Note 3)1.30A
LX1 Leakage CurrentVPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V-10+10µA
SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA2.4632.537REG2 Voltage AccuracyFB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA3.253.35V
FB2 Voltage AccuracyFB2 used with external resistors, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.2311.269V
FB2 Input CurrentFB2 used with external resistors, VFB2 = 1.25V100nA
Dropout VoltageLoad = 900mA (Note 1)380mV
ILX2 = -180mA0.375p-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.425Ω
ILX2 = -180mA0.25n-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.275Ω
p-Channel Current-Limit Threshold-1.1-1.50A
OUT2 Maximum Output Current2.6V ≤ VPV2 ≤ 5.5V (Note 3)0.9A
LX2 Leakage CurrentVPV2 = 5.5V, LX2 = GND or PV2, VON2 = 0V-10+10µA
ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINMAXUNITS
SYNCHRONOUS-BUCK PWM REG3

REG3 Output Voltage AccuracyREG3 from 0.7V to 1.475V,
2.6V ≤ VPV3 ≤ 5.5VLoad = 0 to 500mA-1.5+1.5%
ILX3 = -180mA0.375p-Channel On-ResistanceILX2 = -180mA, VPV3 = 2.6V0.425Ω
ILX3 = 180mA0.25n-Channel On-ResistanceILX3 = 180mA, VPV3 = 2.6V0.275Ω
p-Channel Current-Limit Threshold-0.60-0.85A
OUT3 Maximum Output Current2.6V ≤ VPV3 ≤ 5.5V (Note 3)0.5A
LX3 Leakage CurrentVPV3 = 5.5V, LX3 = GND or PV2, VON3 = 0V-10+10µA
LDOs V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current35mA
V7 Output Current30mA
REG4 Voltage AccuracyLoad = 0.1mA to 35mA1.2541.346V
REG5 Voltage AccuracyLoad = 0.1mA to 35mA1.0611.139V
IN45, IN6 Input Voltage Range2.45.5V
1.8V setting, load = 0.1mA to 35mA1.7371.863
2.5V setting, load = 0.1mA to 35mA2.4122.588REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)
3.0V setting, load = 0.1mA to 35mA2.8953.105
V1 and V2 SLEEP Output Voltage
AccuracySet to same output voltage as REG1 and REG2-3.5+3.5%
V1 and V2 SLEEP Dropout VoltageLoad = 20mA150mV
V6 Dropout Voltage3V m od e, l oad = 30m A; 2.5V m od e, l oad = 30m A200mV
V7 Switch Voltage DropLoad = 20mA, VBKBT = VV1 = 3.0V200mV
V4, V5, V6 Output Current Limit 40 mA
BKBT Leakage 1 µA
OSCILLATOR

PWM Switching Frequency0.931.07MHz
SUPERVISORY/MANAGEMENT FUNCTIONS

Rising9297POK Trip Threshold (Note 4)Falling88.592.5%
LBI = IN (for preset)3.513.69LBI Threshold (Falling)Hysteresis is 5% (typ)With resistors at LBI0.981.02V
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
PARAMETERCONDITIONSMINMAXUNITS

DBI = IN (for preset)2.9933.307DBI Threshold (Falling)Hysteresis is 5% (typ)With resistors at LBI1.2081.256V
RSO Threshold (Falling)Voltage on REG7, hysteresis is 5% (typ)2.252.60V
RSO Deassert Delay6269ms
LBI Input Bias Current-50nA
DBI Input Bias Current75nA
LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level2.6V ≤ V7 ≤ 5.5V, sinking 1mA0.4V
LBO, DBO, POK, RSO, SDA Output
Low LevelV7 = 1V, sinking 100µA0.4V
LBO, DBO, POK, RSO Output-High
Leakage CurrentPin = 5.5V0.2µA
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level2.6V ≤ VIN ≤ 5.5V1.6V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level2.6V ≤ VIN ≤ 5.5V0.4V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage CurrentPin = GND, 5.5V-1+1µA
SERIAL INTERFACE

Clock Frequency400kHz
Bus Free Time Between START and
STOP1.3µs
Hold Time Repeated START
Condition0.6µs
CLK Low Period1.3µs
CLK High Period0.6µs
Setup Time Repeated START
Condition0.6µs
DATA Hold Time0µs
DATA Setup Time100ns
Setup Time for STOP Condition0.6µs
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
Note 1:
Dropout voltage is guaranteed by the p-channel switch resistance and assumes a maximum inductor resistance of 45mΩ.
Note 2:
The PWM-skip-mode transition has approximately 10mA of hysteresis.
Note 3:
The maximum output current is guaranteed by the following equation:
where:
and RN = n-channel synchronous rectifier RDS(ON)
RP = p-channel power switch RDS(ON)
RL = external inductor ESR
IOUT(MAX) = maximum required load current
f = operating frequency minimum
L = external inductor value
ILIMcan be substituted for IOUT(MAX) (desired) when solving for D. This assumes that the inductor ripple current is
small relative to the absolute value.
Note 4:
POK only indicates the status of supplies that are enabled (except V7). When a supply is turned off, POK does not trigger
low. When a supply is turned on, POK immediately goes low until that supply reaches regulation. POK is forced low when all
supplies (except V7) are disabled.
Note 5:
Specifications to -40°C are guaranteed by design, not production tested.VIRRRR
OUTOUTMAXNLOUTMAXNP++VDxLDxL
OUT
LIMOUT
max()=−−1
ELECTRICAL CHARACTERISTICS (continued)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
Typical Operating Characteristics

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
0.1110100100010,000
REG1 3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT

MAX8588 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG2 2.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX8588 toc02
LOAD CURRENT (mA)
EFFICIENCY (%)VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG3 1.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX8588 toc03
LOAD CURRENT (mA)
EFFICIENCY (%)VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG3 1.3V OUTPUT WITH FORCED-PWM
EFFICIENCY vs. LOAD CURRENT
MAX8588 toc04
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 5.0V
VIN = 4.0V
REG2 SLEEP LDO 2.5V OUTPUT
EFFICIENCY vs. LOAD CURRENT
MAX8588 toc06
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6VVIN = 4.0V
VIN = 5.0V
REG1 SLEEP LDO 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT

MAX8588 toc05
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 4.0V
VIN = 5.0V
QUIESCENT CURRENT
vs. SUPPLY VOLTAGE
MAX8588 toc07
INPUT VOLTAGE (V)
INPUT CURRENT (
BKBT BIASED AT 3.6V
V1, V2, AND V3 ON
V1 AND V2 ON
V1 ON
V1 AND V2 SLEEP
V1 SLEEP
ALL BUT V7 OFF
120
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones

DROPOUT VOLTAGE
vs. LOAD CURRENT
MAX8588 toc08
LOAD CURRENT (mA)
DROPOUT VOLTAGE (mV)
REG1 3.3V OUTPUT
CHANGE IN OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX8588 toc09
LOAD CURRENT (mA)
CHANGE IN OUTPUT VOLTAGE (mV)
VIN = 3.6V
REG1 3.3V OUTPUT
REG3 1.3V OUTPUT
REG2 2.5V OUTPUT
SWITCHING FREQUENCY
vs. SUPPLY VOLTAGE
MAX8588 toc10
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
TA = -40°C
TA = +85°C
TA = +25°C
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX8588 toc11
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
REG1 SWITCHING WAVEFORMS
WITH 800mA LOAD

MAX8588 toc12
400ns/div
500mA/div
10mv/div
AC-COUPLED
2V/div
VLX1
IL1
REG1 SWITCHING WAVEFORMS
WITH 10mA LOAD

MAX8588 toc13
20μs/div
500mA/div
50mv/div
AC-COUPLED
2V/div
VLX1
IL1ypical Operating Characteristics (continued)
(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
REG3 SWITCHING WAVEFORMS
WITH 250mA LOAD

MAX8588 toc14
400ns/div
500mA/div
10mv/div
AC-COUPLED
2V/div
IL3
VLX3
REG3 PULSE-SKIP SWITCHING
WAVEFORMS WITH 10mA LOAD

MAX8588 toc15
10μs/div
500mA/div
10mv/div
AC-COUPLED
2V/divVLX3
IL3
REG3 FORCED-PWM SWITCHING
WAVEFORMS WITH 10mA LOAD

MAX8588 toc16
400ns/div
0mA
500mA/div
10mv/div
AC-COUPLED
2V/div
VLX3
IL3
V7 AND RSO
STARTUP WAVEFORMS

MAX8588 toc17
10ms/div
2V/div
2V/div
2V/div
RSO
VIN
SYS_EN STARTUP WAVEFORMS

MAX8588 toc18
2ms/div
2V/div
2V/div
2V/div
2V/div
VEN1
AND
VEN2
VPOK
PWR_EN STARTUP WAVEFORMS

MAX8588 toc19
1ms/div
2V/div
2V/div
2V/div
2V/div
2V/div
VEN3
AND
VEN45
VPOK
Typical Operating Characteristics (continued)

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
REG1 LOAD-TRANSIENT RESPONSE

MAX8588 toc20
200μs/div
100mV/div
AC-COUPLED
ILOAD1
200mA/div
REG2 LOAD-TRANSIENT RESPONSE

MAX8588 toc21
200μs/div
100mV/div
AC-COUPLED
ILOAD2
200mA/div
REG3 LOAD-TRANSIENT RESPONSE

MAX8588 toc22
200μs/div
100mV/div
AC-COUPLED
ILOAD3
200mA/div
REG3 OUTPUT VOLTAGE CHANGING FROM
1.3V TO 1.0V WITH DIFFERENT VALUES OF CRAMP

MAX8588 toc23
200μs/div
CRAMP = 2200pF
CRAMP = 1500pF
CRAMP = 1000pF
CRAMP = 330pF
REG6 USIM TRANSITIONS

MAX8588 toc24
10μs/div
500mV/divV6
2.5V TO 3.0V
1.8V TO 2.5V
0 TO 1.8Vypical Operating Characteristics (continued)
(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
Pin Description
PINNAMEFUNCTION
LBI
Dual-Mode™, Low-Battery Input. Connect to IN to set the low-battery threshold to 3.6V (no resistors needed).
Connect LBI to a resistor-divider for an adjustable LBI threshold. When IN is below the set threshold, LBO
output switches low. LBO is deactivated and forced low when IN is below the dead-battery (DBI) threshold
and when all REGs are disabled.CC1REG1 Compensation Node. Connect a series resistor and capacitor from CC1 to GND to compensate the
regulation loop. See the Compensation and Stability section.FB1REG1 Feedback Input. Connect FB1 to GND to set V1 to 3.3V. Connect FB1 to external feedback resistors
for other output voltages.BKBTInput Connection for Backup Battery. This input can also accept the output of an external boost converter.
5V7
Also known as VCC_BATT. V7 is always active if main or backup power is present. It is the first regulator that
powers up. V7 has two states:
1) V7 tracks V1 if ON1 is high and V1 is in regulation.
2) V7 tracks VBKBT when ON1 is low or V1 is out of regulation.
6V1REG1 Voltage-Sense Input. Connect directly to the REG1 output voltage. The output voltage is set by FB1 to
either 3.3V or adjustable with resistors.SLPINInp ut to V 1 and V 2 S l eep Reg ul ator s. The i np ut to the stand b y r eg ul ator s at V 1 and V 2. C onnect S LP IN to IN .
8V2REG2 Voltage-Sense Input. Connect directly to the REG2 output voltage. The output voltage is set by FB2 to
either 3.3V/2.5V or adjustable with resistors.FB2REG2 Feedback Input. Connect to GND to set V2 to 2.5V on all devices. Connect FB2 to IN to set V2 to 3.3V.
Connect FB2 to external feedback resistors for other voltages.CC2REG2 Compensation Node. Connect a series resistor and capacitor from CC2 to GND to compensate the
regulation loop. See the Compensation and Stability section. POK
Power-OK Output. Open-drain output that is low when any of the V1–V6 outputs are below their regulation
threshold. When all activated outputs are in regulation, POK is high impedance. POK maintains a valid low
output with V7 as low as 1V. POK does not flag an out-of-regulation condition while REG3 is transitioning
between voltages set by serial programming. POK also does not flag for any REG channel that has been
turned off; however, if all REG channels are off (V1–V6), then POK is forced low. If IN < UVLO, then POK is
low. POK is expected to connect to nVCC_FAULT.SCLSerial Clock InputSDA
Serial Data Input. Serial data programs the REG3 (core) and REG6 (VCC_USIM) voltage. REG3 and REG6
can be programmed even when off, but at least one of the ON_ pins must be logic-high to activate the serial
interface. On power-up, REG3 defaults to 1.3V and REG6 defaults to 0V.PWM3Force V3 to PWM at All Loads. Connect PWM3 to GND for normal operation (skip mode at light loads). Drive
or connect high for forced-PWM operation at all loads for V3 only.LBOLow-Battery Output. Open-drain output that goes low when IN is below the threshold set by LBI.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
Pin Description (continued)
PINNAMEFUNCTION
PV2REG2 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.LX2REG2 Switching Node. Connects to REG2 inductor.PG2REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.INMain Battery Input. This input provides power to the IC.RAMPV3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100kΩ. FB3 regulates to 1.28 x VRAMP.GNDAnalog GroundREFReference Output. Output of the 1.25V reference. Bypass to GND with a 0.1µF or greater capacitor.BYPLow-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01µF capacitor from BYP to GND.DBO
Dead or Missing Battery Output. DBO is an open-drain output that goes low when IN is below the threshold
set by DBI. DBO does not deactivate any regulator outputs. DBO is expected to connect to nBATT_FAULT
on Intel CPUs.ON2
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1,
ON2, and ON6 are connected to SYS_EN.ON4
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON4
is connected to PWR_EN.V4Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.IN45Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to VIN.V5Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.ON5
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX8588 soft-starts the REG5 output. ON5
has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON5 is connected to PWR_EN.PG3REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.LX3REG3 Switching Node. Connects to the REG3 inductor.PV3REG3 Power Input. Bypass to PG3 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN
must connect together externally.ON3
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
MAX8588
High-Efficiency, Low-IQPMIC with
Dynamic Core for PDAs and Smartphones
Pin Description (continued)
PINNAMEFUNCTION
SRADSerial Address Bit. SRAD allows the serial address to be changed in case it conflicts with another serial
device. If SRAD = GND, A1 = 0. If SRAD = IN, A1 = 1.RSOOpen-Drain Reset Output. Deasserts when V7 exceeds 2.55V (typ rising). Has 65ms delay before release.
RSO is expected to connect to nRESET on the CPU.MRManual Reset Input. A low input at MR causes the RSO output to go low and also resets the V3 output to its
default 1.3V setting. MR impacts no other functions.CC3REG 3 Compensation Node. Connect a series resistor and capacitor from CC3 to GND to compensate the
regulation loop. See the Compensation and Stability section.FB3REG3 Feedback-Sense Input. Connect directly to the REG3 output voltage. Output voltage is set by the serial
interface.ON6
On/Off Input for REG6. Drive high to turn on. When enabled, the REG6 output activates. ON6 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that ON1,
ON2, and ON6 are connected to SYS_EN.V6Also known as VCC_USIM. Linear-regulator output. This voltage is programmable through the I2C interface to
0V, 1.8V, 2.5V, or 3.0V. The default voltage is 0V. REG6 is activated when ON6 is high.IN6Power Input to the V6 LDO. Typically connected to V1, but can also connect to IN.PG1REG1 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.LX1REG1 Switching Node. Connects to the REG1 inductor.PV1REG1 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and IN
must connect together externally.ON1
On/Off Input for REG1. Drive high to turn on REG1. When enabled, the REG1 output soft-starts. ON1 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 connect to SYS_EN.SLP
Sleep Input. SLP selects which regulators ON1 and ON2 turn on. SLP = high is normal operation (ON1 and
ON2 are the enables for the V1 and V2 DC-DC converters). SLP = low is sleep operation (ON1 and ON2 are
the enables for the V1 and V2 LDOs).DBIDual-Mode, Dead-Battery Input. Connect DBI to IN to set the dead-battery falling threshold to 3.15V (no
resistors needed). Connect DBI to a resistor-divider for an adjustable DBI threshold.EPExposed Metal Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to the appropriate ground pins.
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