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MAX837EUSMAXIMN/a1883avaiPLASTIC ENCAPSULATED DEVICES
MAX837EUS |MAX837EUSMAXN/a520avaiPLASTIC ENCAPSULATED DEVICES


MAX837EUS ,PLASTIC ENCAPSULATED DEVICES MAX837EUS Rev. B RELIABILITY REPORT FOR MAX837EUS PLASTIC ENCAPSU ..
MAX837EUS ,PLASTIC ENCAPSULATED DEVICES MAX837EUS Rev. B RELIABILITY REPORT FOR MAX837EUS PLASTIC ENCAPSU ..
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MAX837EUS
PLASTIC ENCAPSULATED DEVICES
MAX837EUS Rev. B RELIABILITY REPORT FOR MAX837EUS PLASTIC ENCAPSULATED DEVICES November 11, 2001 MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by Reviewed by Jim Pedicord Bryan J. Preeshl Quality Assurance Quality Assurance Reliability Lab Manager Executive Director
Conclusion The MAX837 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality and reliability standards. Table of Contents I. ........Device Description V. ........Quality Assurance Information II. ........Manufacturing Information VI. .......Reliability Evaluation III. .......Packaging Information IV. .......Die Information ......Attachments I. Device Description A. General The MAX837 micropower voltage monitor contains a 1.204V precision bandgap reference and a comparator in a SOT143 package. The MAX837 has a push-pull output driver. Two external resistors set the trip threshold voltage. B. Absolute Maximum Ratings Item Rating IN, OUT to GND -0.3V to (VCC + 0.3V) Input Current VCC 20mA IN 10mA Output Current, OUT 20mA Rate of Rise, VCC 100V/µs Operating Temperature Range -40°C to +85°C Storage Temperature Range -65°C to +150°C Lead Temp. (10 sec.) +300°C Power Dissipation 4-Lead SOT143 320mW Derates above +70°C 4-Lead SOT143 4.00mW/°C
II. Manufacturing Information A. Description/Function: 4-Pin Micropower Voltage Monitor B. Process: S3 (Standard 3 micron silicon gate CMOS) C. Number of Device Transistors: 54 D. Fabrication Location: California or Oregon, USA E. Assembly Location: Malaysia or Thailand F. Date of Initial Production: November, 1996 III. Packaging Information A. Package Type: 4 Lead SOT-143 B. Lead Frame: Alloy 42 or Copper C. Lead Finish: Solder Plate D. Die Attach: Silver-filled Epoxy E. Bondwire: Gold (1 mil dia.) F. Mold Material: Epoxy with silica filler G. Assembly Diagram: Buildsheet # 05-1601-0019 H. Flammability Rating: Class UL94-V0 I. Classification of Moisture Sensitivity per JEDEC standard JESD22-A112: Level 1 IV. Die Information A. Dimensions: 44 x 31 mils B. Passivation: Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) C. Interconnect: Aluminum/Si (Si = 1%) D. Backside Metallization: None E. Minimum Metal Width: 3 microns (as drawn) F. Minimum Metal Spacing: 3 microns (as drawn) G. Bondpad Dimensions: 5 mil. Sq. H. Isolation Dielectric: SiO2
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager) Bryan Preeshl (Executive Director) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects. C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure Rate (l) is calculated as follows: l = 1 = 1.83 (Chi square value for MTTF upper limit) MTTF 192 x 4389 x 160 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV l = 6.79 x 10-9 l = 6.79 F.I.T. (60% confidence level @ 25°C) This low failure rate represents data collected from Maxim’s reliability monitor program. In addition to routine production Burn-In, Maxim pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Spec. # 06-5173) shows the static Burn-In circuit. Maxim also performs quarterly 1000 hour life test monitors. This data is published in the Product Reliability Report (RR-1L). B. Moisture Resistance Tests Maxim pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85°C/85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The MS09-1 die type has been found to have all pins able to withstand a transient pulse of ±800V, per Mil-Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of ±200mA.
Table 1
Reliability Evaluation Test Results MAX837EUS TEST ITEM TEST CONDITION FAILURE SAMPLE NUMBER OF IDENTIFICATION SIZE FAILURES Static Life Test (Note 1) Ta = 135°C DC Parameters 180 0 Biased & functionality Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121°C DC Parameters 159 0 P = 15 psi. & functionality RH= 100% Time = 96hrs. 85/85 Ta = 85°C DC Parameters 77 0 RH = 85% & functionality Biased Time = 1000hrs. Mechanical Stress (Note 2) Temperature -65°C/150°C DC Parameters 77 0 Cycle 1000 Cycles &functionality Method 1010 Note 1: Life Test Data may represent plastic D.I.P. qualification lots for the package. Note 2: Generic Package/Process information.
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/ 1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 Pin combinations to be tested. a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. b. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. c. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
TERMINAL B
TERMINAL A
CURRENT
PROBE
(NOTE 6)
R = 1.5kWW
C = 100pf
SHORT
R2
S2 R1
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