MAX7360ETL+ ,I²C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD ProtectionApplicationsTOSCL SWITCHFCPORT7SDACell PhonesPORT6INTIPDAsINTKMAX7360Handheld GamesPORT0Portable Co ..
MAX7367EUP+ ,4-Channel I²C Switches/MultiplexerFeatures♦ Four-Channel, Bidirectional Bus ExpansionThe MAX7367/MAX7368/MAX7369 bidirectional, four- ..
MAX7367EUP+ ,4-Channel I²C Switches/MultiplexerApplications+A0 1 20 VDDServersA1 2 19 SDARAIDRESET 3 18 SCLCellular PhonesBase Stations INT0 4 MAX ..
MAX7369EUP+ ,4-Channel I²C Switches/MultiplexerMAX7367/MAX7368/MAX736919-0644; Rev 2; 2/0924-Channel I C Switches/Multiplexer
MAX7369EUP+T ,4-Channel I²C Switches/MultiplexerFeatures♦ Four-Channel, Bidirectional Bus ExpansionThe MAX7367/MAX7368/MAX7369 bidirectional, four- ..
MAX736CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM Regulatorsapplications.
The MAX736/MAX737/MAX739 have fixed outputs of -12V,
-15V, and -5V respectively. ..
MB6021A ,SINGLE CHIP CODEC WITH FILTERSFUJITSU hTCRoirLECTR()NTCS 31.5 D, " 37u=17aa 001.71.55 =1 "hu
April 1990
Edition 3.0
DA TA ..
MB6021AP ,SINGLE CHIP CODEC WITH FILTERSFUNCTIONAL DESCRIPTION
The simplified
MB6022 , Product Summary Prototyping Kits
MB6022 , Product Summary Prototyping Kits
MB6022A ,SINGLE CHIP CODEC WITH FILTERSFUNCTIONAL DESCRIPTION
The simplified
MB6M ,MINIATURE GLASS PASSIVATED SINGLE-PHASE BRIDGE RECTIFIERThermal Characteristics (TA = 25°C unless otherwise noted)Parameter Symbol MB2M MB4M MB6M UnitDevic ..
MAX7360ETL+
I²C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
EVALUATION KIT AVAILABLE General Description
The MAX7360 I2C-interfaced peripheral provides micro-
processors with management of up to 64 key switches,
with an additional eight LED drivers/GPIOs that feature
constant-current, PWM intensity control, and rotary
switch control options.
The key-switch drivers interface with metallic or resis-
tive switches with on-resistances up to 5kI. Key inputs
are monitored statically, not dynamically, to ensure
low-EMI operation. The MAX7360 features autosleep
and autowake modes to further minimize the power
consumption of the device. The autosleep feature puts
the device in a low-power state (1FA typ) after a sleep
timeout period. The autowake feature configures the
MAX7360 to return to normal operating mode from sleep
upon a keypress.
The key controller debounces and maintains a FIFO of
keypress and release events (including autorepeat, if
enabled). An interrupt (INTK) output can be configured
to alert keypresses, as they occur, or at maximum rate.
There are eight open-drain I/O ports, which can be used
to drive LEDs. The maximum constant-current level for
each open-drain port is 20mA. The intensity of the LED
on each open-drain port can be individually adjusted
through a 256-step PWM control. An input port pair
(PORT6, PORT7) can be configured to accept 2-bit gray
code inputs from a rotary switch. In addition, if not used
for key-switch control, up to six column pins can be used
as general-purpose open-drain outputs (GPOs) for LED
drive or logic control.
The MAX7360 is offered in a 40-pin (5mm x 5mm)
thin QFN package with an exposed pad, and a small
36-bump wafer level package (WLP) for cell phones,
pocket PCs, and other portable consumer electronic
applications. The MAX7360 operates over the -40NC to
+85NC extended temperature range.
Applications
Cell Phones
PDAs
Handheld Games
Portable Consumer Electronics
Printers
Instrumentation
Features
S Integrated ESD Protection ±8kV IEC 61000-4-2 Contact Discharge ±15kV IEC 61000-4-2 Air-Gap Discharge
S +14V Tolerant, Open-Drain I/O Ports Capable of
Constant-Current LED Drive
S Rotary Switch-Capable Input Pair (PORT6, PORT7)
S 256-Step PWM Individual LED Intensity Control
S Individual LED Blink Rates and Common LED
Fade In/Out Rates from 256ms to 4096ms
S FIFO Queues Up to 16 Debounced Key Events
S User-Configurable Key Debounce (9ms to 40ms)
S Keyscan Uses Static Matrix Monitoring for Low
EMI Operation
S +1.62V to +3.6V Operation
S Monitors Up to 64 Keys
S Key-Switch Interrupt (INTK) on Each Debounced
Event/FIFO Level, or End of Definable Time Period
S Port Interrupt (INTI) for Input Ports for Special-Key
Functions
S 400kbps, +5.5V Tolerant 2-Wire Serial Interface
with Selectable Bus Timeout
S Four I2C Address Choices
Simplified Block Diagram
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configurations appear at end of data sheet.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX7360ETL+-40°C to +85°C40 TQFN-EP*
MAX7360EWX+-40°C to +85°C36 WLP
MAX7360
AD0
PORT7
PORT6
PORT0
COL_(8x)
ROW_(8x)
INTK
INTI
SDA
SCL
ROTARY
SWITCH
+14V
8 x 8
+1.8V
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VCC to GND .............................................................-0.3V to +4V
COL0–COL7, ROW0–ROW7 to GND ......................-0.3V to +4V
SDA, SCL, AD0, INTI, INTK to GND ........................-0.3V to +6V
PORT0–PORT7 to GND .........................................-0.3V to +16V
All Other Pins to GND ................................-0.3V to (VCC + 0.3V)
DC Current on PORT0–PORT7, COL2–COL7 ....................25mA
GND Current .......................................................................80mA
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 22.2mW/NC above +70NC) ..................1777mW
WLP (derate 21.7mW/NC above +70NC) ....................1739mW
Operating Temperature Range ..........................-40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................-65NC to +150NC
ESD Protection
Human Body Model (RD = 1.5kI, CS = 100pF)
All Pins .............................................................................Q2kV
IEC 61000-4-2 (RD = 330I, CS = 150pF)
Contact Discharge
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND ....Q8kV
Air-Gap Discharge
ROW0–ROW7, COL0–COL7, PORT0–PORT7 to GND ..Q15kV
Lead Temperature (TQFN only; soldering, 10s) ..............+300NC
Soldering Temperature (reflow) .......................................+260NC
ELECTRICAL CHARACTERISTICS
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 2, 3)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a single-
layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
TQFN
Junction-to-Ambient Thermal Resistance (BJA) .........45NC/W
Junction-to-Case Thermal Resistance (BJC) ................2NC/W
WLP
Junction-to-Ambient Thermal Resistance (BJA) WLP .46NC/W
PACKAGE THERMAL CHARACTERISTICS(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Supply VoltageVCC1.623.33.6V
External Supply Voltage
PORT0–PORT7VPORT_14V
Operating Supply CurrentICC
All key switches open, oscillator running,
COL2–COL7 configured as key switches,
VPORT_ = VCC50
N keys pressed34 +
20 x N
Sleep-Mode Supply CurrentISL1.33FA
Key-Switch Source CurrentIKEY2035FA
Key-Switch Source VoltageVKEY0.430.5V
Key-Switch ResistanceRKEY(Note 4)5kI
Startup Time from ShutdowntSTART22.4ms
Output Low Voltage
COL2–COL7VOLISINK = 10mA0.5V
Oscillator Frequency (PWM
Clock)fOSCTA = +25NC, VCC = +2.61V125128131
kHz
TA = TMIN to TMAX, VCC P 3.6V102164
Oscillator Frequency VariationDfOSCTA = +25NC-7+14%
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 2, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GPIO SPECIFICATIONS
Input High Voltage
PORT0–PORT7VIH0.7 x
VCCV
Input Low Voltage
PORT0–PORT7VIL0.3 x
VCCV
Input Leakage Current
PORT0–PORT7IINVIN P VCC-0.25+0.25FAVCC < VIN-1+5
Output Low Voltage
PORT0–PORT7VOLISINK < 20mA0.6V
Input Capacitance
PORT0–PORT720pF
10mA Port Sinking Current
PORT0–PORT7
VCC = +1.62V to +3.6V, TA = +25NC8.5511.52VCC = +3.3V, VOL = +1V8.679.7610.51
20mA Port Sinking Current
PORT0–PORT7
VCC = +1.62V to +3.6V, TA = +25NC19.4021.33mA
VCC = +3.3V, VOL = +1V19.552020.69
Port Sink Current VariationVCC = +3.3V, VOL = +1V, TA = +25NC,
20mA output mode Q1.5 Q2.4%
Output Logic-Low Voltage
INTI, INTKISINK = 10mA0.6V
PWM FrequencyfPWMDerived from oscillator clock500Hz
SERIAL-INTERFACE SPECIFICATIONS
Input High Voltage
SDA, SCL, AD0VIH0.7 x
VCCV
Input Low Voltage
SDA, SCL, AD0VIL0.3 x
VCCV
Input Leakage Current
SDA, SCL, AD0IINVIN P VCC-0.25+0.25FAVIN > VCC-0.5+0.5
Output Low Voltage
SDAVOLISINK = 6mA0.6V
Input Capacitance
SDA, SCL, AD0CIN10pF
I2C TIMING SPECIFICATIONS
SCL Serial-Clock FrequencyfSCLBus timeout disabled0400kHz
Bus Free Time Between a STOP
and START ConditiontBUF1.3Fs
Hold Time (Repeated) START
ConditiontHD, STA0.6Fs
Repeated START Condition
Setup TimetSU, STA0.6Fs
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.62V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC.) (Notes 2, 3)
Note 2: All parameters are tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at VCC or GND.
Note 4: Guaranteed by design.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 6: Cb = total capacitance of one bus line in pF. tR and tF measured between +0.3VCC and +0.7VCC.
Note 7: ISINK ≤ 6mA.
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Hold TimetHD, DAT(Note 5)0.9Fs
Data Setup TimetSU, DAT100ns
SCL Clock Low PeriodtLOW1.3Fs
SCL Clock High PeriodtHIGH0.7Fs
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Notes 4, 6)20 +
0.1Cb300ns
Fall Time of Both SDA and SCL
Signals, ReceivingtF(Notes 4, 6)20 +
0.1Cb300ns
Fall Time of SDA Signal,
TransmittingtF, TX(Notes 4, 7)20 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Notes 4, 8)50ns
Capacitive Load for Each Bus
LineCb(Note 4)400pF
I2C-Interfaced Key-Switch Controller and LED
Driver/GPIOs with Integrated ESD Protection
MAX7360
Typical Operating Characteristics
(VCC = +2.5V, TA = +25NC, unless otherwise noted.)
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (COL2–COL7)MAX7360 toc01
SINK CURRENT (mA)
OUTPUT VOLTAGE (mV)105
TA = +85NC
TA = +25NC
TA = -40NC
VCC = 2.4V
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (COL2–COL7)MAX7360 toc02
SINK CURRENT (mA)
OUTPUT VOLTAGE (mV)105
TA = +25°C
TA = -40°C
VCC = 3.0V
TA = +85°C
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (COL2–COL7)MAX7360 toc03
SINK CURRENT (mA)
OUTPUT VOLTAGE (mV)105
TA = +25°C
TA = -40°C
VCC = 3.6V
TA = +85°C
KEY-SWITCH SOURCE CURRENT
vs. SUPPLY VOLTAGEMAX7360 toc05
SUPPLY VOLTAGE (V)
KEY-SWITCH SOURCE CURRENT (A)
VCOL0 = O
TA = -40NC, +25NC
TA = +25NC
TA = -40NC
TA = -40NC, +85NC
TA = +85NC
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX7360 toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (A)
TA = -40NC
TA = +25NC
TA = +85NC
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGEMAX7360 toc07
SINK CURRENT (mA)
TA = -40NC
VCC = 2.4V
TA = +25NC
TA = +85NC
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGEMAX7360 toc09
SINK CURRENT (mA)
TA = -40NC
VCC = 3.6V
TA = +25NC
TA = +85NC
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGEMAX7360 toc08
SINK CURRENT (mA)
1.52.01.00.53.02.5VCC = 3.0V
TA = -40NC
TA = +25NC
TA = +85NC
SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX7360 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (A)
TA = +85NC
AUTOSLEEP = OFF
TA = -40NC
TA = +25NC
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Pin Description
PINNAMEFUNCTIONTQFNWLPA6ROW0Row Input from Key Matrix. Leave ROW0 unconnected or connect to GND if unused.B6ROW1Row Input from Key Matrix. Leave ROW1 unconnected or connect to GND if unused.C4ROW2Row Input from Key Matrix. Leave ROW2 unconnected or connect to GND if unused.C6ROW3Row Input from Key Matrix. Leave ROW3 unconnected or connect to GND if unused.
5, 15, 25,
B4, C5, D2, GNDGroundD6ROW4Row Input from Key Matrix. Leave ROW4 unconnected or connect to GND if unused.D5ROW5Row Input from Key Matrix. Leave ROW5 unconnected or connect to GND if unused.E6ROW6Row Input from Key Matrix. Leave ROW6 unconnected or connect to GND if unused.D4ROW7Row Input from Key Matrix. Leave ROW7 unconnected or connect to GND if unused.
10, 20, 27,
30, 40C2N.C.No Connection. Not internally connected. Leave unconnected.F6COL0Column Output to Key Matrix. Leave COL0 unconnected if unused.E5COL1Column Output to Key Matrix. Leave COL1 unconnected if unused.F5COL2Column Output to Key Matrix. Leave COL2 unconnected if unused. COL2 can be
configured as a GPO (see Table 9 in the Register Tables section).F4COL3Column Output to Key Matrix. Leave COL3 unconnected if unused. COL3 can be
configured as a GPO (see Table 9 in the Register Tables section).F3COL4Column Output to Key Matrix. Leave COL4 unconnected if unused. COL4 can be
configured as a GPO (see Table 9 in the Register Tables section).E3COL5Column Output to Key Matrix. Leave COL5 unconnected if unused. COL5 can be
configured as a GPO (see Table 9 in the Register Tables section).F2COL6Column Output to Key Matrix. Leave COL6 unconnected if unused. COL6 can be
configured as a GPO (see Table 9 in the Register Tables section).F1COL7Column Output to Key Matrix. Leave COL7 unconnected if unused. COL7 can be
configured as a GPO (see Table 9 in the Register Tables section).E2SDAI2C-Compatible, Serial-Data I/OE1SCLI2C-Compatible, Serial-Clock InputD3INTKActive-Low Key-Switch Interrupt Output. INTK is open drain and requires a pullup
resistor.
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Pin Description (continued)
PINNAMEFUNCTIONTQFNWLPD1INTIActive-Low GPI Interrupt Output. INTI is open drain and requires a pullup resistor.C1VCCPositive Supply Voltage. Bypass VCC to GND with a 0.1FF or higher ceramic capacitor.B1AD0Address Input. AD0 selects up to four device slave addresses (Table 3).A1I.C.Internally Connected. Connect to GND for normal operation.B2PORT0GPIO Port. Open-drain I/O rated at +14V. PORT0 can be configured as a constant-
current output.A2PORT1GPIO Port. Open-drain I/O rated at +14V. PORT1 can be configured as a constant-
current output.B3PORT2GPIO Port. Open-drain I/O rated at +14V. PORT2 can be configured as a constant-
current output.A3PORT3GPIO Port. Open-drain I/O rated at +14V. PORT3 can be configured as a constant-
current output.A4PORT4GPIO Port. Open-drain I/O rated at +14V. PORT4 can be configured as a constant-
current output.C3PORT5GPIO Port. Open-drain I/O rated at +14V. PORT5 can be configured as a constant-
current output.A5PORT6GPIO Port. Open-drain I/O rated at +14V. PORT6 can be configured as a constant-
current output, or a rotary switch input.B5PORT7GPIO Port. Open-drain I/O rated at +14V. PORT7 can be configured as a constant-
current output, or a rotary switch input.—EPExposed Pad (TQFN only). EP is internally connected to GND. Connect EP to a ground
plane to increase thermal performance.
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Functional Block Diagram
Detailed Description
The MAX7360 is a microprocessor peripheral low-noise
key-switch controller that monitors up to 64 key switches
with optional autorepeat, and key events that are pre-
sented in a 16-byte FIFO. The MAX7360 also features
eight open-drain GPIOs configured for digital I/O or
constant-current output for LED applications up to +14V.
The MAX7360 features an automatic sleep mode and
automatic wakeup that further reduce supply current
consumption. The MAX7360 can be configured to enter
sleep mode after a programmable time following a key
event. The FIFO content is maintained and can be read
in sleep mode. The MAX7360 does not enter autosleep
when a key is held down. The autowake feature takes
the MAX7360 out of sleep mode following a keypress
event. Enable/disable autosleep and autowake through
the configuration register (Table 8).
To prevent overloading the microprocessor with too
many interrupts, interrupt requests are issued on a
programmable number of FIFO entries, and/or after a
set period of time (Table 10). The key-switch status is
checked by reading the key-switch FIFO. A 1-byte read
access returns both the next key event in the FIFO (if
there is one) and the FIFO status. INTK functions as an
open-drain general-purpose output (GPO) capable of
driving an LED if key-switch interrupts are not required.
Up to six of the key-switch outputs function as open-
drain GPOs capable of driving additional LEDs when
the application requires fewer keys to be scanned. For
each key-switch output used as a GPO, the number of
monitored key switches reduces by eight.
Initial Power-Up
On power-up, all control registers are set to power-up
values and the MAX7360 is in sleep mode (Table 1).
128kHz
OSCILLATOR
PORBUS
TIMEOUT
I2C
INTERFACE
CONTROL
REGISTERS
FIFO
KEY
SCAN
CURRENT
SOURCE
COLUMN
DRIVES
OPEN-
DRAIN
ROW
DRIVES
COLUMN ENABLE
GPO ENABLE
ROW ENABLE
CURRENT DETECT
COL0
COL1
COL2*
COL3*
COL4*
COL5*
COL6*
COL7*
PWM
GPIO
LOGIC
PORT GPIO
AND
CONSTANT-
CURRENT
LED DRIVE
LED ENABLE
GPIO ENABLE
GPIO INPUT
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
ROW0
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
INTI
INTK
SDA
SCL
AD0
*GPO
MAX7360
ROTARY
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Table 1. Register Address Map and Power-Up Condition
ADDRESS
CODE
(hex)
READ/
WRITE
POWER-UP
VALUE (hex)
REGISTER
FUNCTIONDESCRIPTION
0x00Read only0x3FKeys FIFORead FIFO key-scan data out
0x01R/W0x0AConfigurationPower-down, key-release enable, autowakeup, and I2C time-
out enable
0x02R/W0xFFDebounceKey debounce time settling and GPO enable
0x03R/W0x00InterruptKey-switch interrupt INTK frequency setting
0x04R/W0xFEGPOCOL2–COL7 and INTK GPO control
0x05R/W0x00Key repeatDelay and frequency for key repeat
0x06R/W0x07SleepIdle time to autosleep
0x40R/W0x00GPIO global con-
figurationRotary switch, GPIO standby, GPIO reset, fade
0x41R/W0x00GPIO controlPORT0–PORT7 input/output control
0x42R/W0x00GPIO debouncePORT0–PORT7 debounce time setting
0x43R/W0xC0GPIO constant-
current settingPORT0–PORT7 constant-current output setting
0x44R/W0x00GPIO output modePORT0–PORT7 output mode control
0x45R/W0x00Common PWMCommon PWM duty-cycle setting
0x46R/W0x00Rotary switch con-
figurationRotary switch interrupt frequency and debounce time setting
0x48Read only0x00I2C timeout flagI2C timeout since last POR
0x49Read only0xFFGPIO input registerPORT0–PORT7 input values
0x4ARead only0x00Rotary switch countSwitch cycles since last read
0x50R/W0x00PORT0 PWMPORT0 individual duty-cycle setting
0x51R/W0x00PORT1 PWMPORT1 individual duty-cycle setting
0x52R/W0x00PORT2 PWMPORT2 individual duty-cycle setting
0x53R/W0x00PORT3 PWMPORT3 individual duty-cycle setting
0x54R/W0x00PORT4 PWMPORT4 individual duty-cycle setting
0x55R/W0x00PORT5 PWMPORT5 individual duty-cycle setting
0x56R/W0x00PORT6 PWMPORT6 individual duty-cycle setting
0x57R/W0x00PORT7 PWMPORT7 individual duty-cycle setting
0x58R/W0x00PORT0 configurationPORT0 interrupt, PWM mode control and blink period setting
0x59R/W0x00PORT1 configurationPORT1 interrupt, PWM mode control and blink period setting
0x5AR/W0x00PORT2 configurationPORT2 interrupt, PWM mode control and blink period setting
0x5BR/W0x00PORT3 configurationPORT3 interrupt, PWM mode control and blink period setting
0x5CR/W0x00PORT4 configurationPORT4 interrupt, PWM mode control and blink period setting
0x5DR/W0x00PORT5 configurationPORT5 interrupt, PWM mode control and blink period setting
0x5ER/W0x00PORT6 configurationPORT6 interrupt, PWM mode control and blink period setting
0x5FR/W0x00PORT7 configurationPORT7 interrupt, PWM mode control and blink period setting
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Key-Scan Controller
Key inputs are scanned statically, not dynamically,
to ensure low-EMI operation. As inputs only toggle in
response to switch changes, the key matrix can be
routed closer to sensitive circuit nodes.
The key-scan controller debounces and maintains a FIFO
of keypress and release events (including autorepeated
keypresses, if autorepeat is enabled). Table 2 shows the
key-switch order. The user-programmable key-switch
debounce time, and autosleep timer, is derived from the
64kHz clock, which in turn is derived from the 128kHz
oscillator. Time delay for autorepeat and key-switch
interrupt is based on the key-switch debounce time.
Keys FIFO Register (0x00)
The keys FIFO register contains the information pertaining
to the status of the keys FIFO, as well as the key events
that have been debounced (see Table 7 in the Register
Tables section). Bits D0–D5 denote which of the 64 keys
have been debounced and the keys are numbered as in
Table 2.
D7 indicates if there is more data in the FIFO, except
when D5:D0 indicate key 63 or key 62. When D5:D0
indicate key 63 or key 62, the host should read one more
time to determine whether there is more data in the FIFO.
Use key 62 and key 63 for rarely used keys. D6 indicates
if it is a keypress or release event, except when D5:D0
indicate key 63 or key 62.
Reading the key-scan FIFO clears the interrupt INTK
depending on the setting of bit D5 in the configuration
register (0x01).
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature, enables key-release detection, enables autowake,
and determines how INTK is deasserted. Write to bit D7
to put the MAX7360 into sleep mode or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7 (see Table 8 in the Register Tables section).
Debounce Register (0x02)
The debounce register sets the time for each debounce
cycle, as well as setting whether the GPO ports are
enabled or disabled. Bits D0–D4 set the debounce time
in increments of 1ms starting at 9ms and ending at 40ms
(see Table 9 in the Register Tables section). Bits D5, D6,
and D7 set which of the GPO ports is enabled. Note the
GPO ports are enabled only in the combinations shown
in Table 9, from all disabled to all enabled.
Key-Switch Interrupt Register (0x03)
The interrupt register contains information related to the
settings of the interrupt request function, as well as the
status of the INTK output, which can also be configured
as a GPO. If bits D0–D7 are set to 0x00, the INTK output
is configured as a GPO that is controlled by bit D1 in the
port register. There are two types of interrupts, the FIFO-
based interrupt and time-based interrupt. Set bits D0–D4
to assert interrupts at the end of the selected number of
debounce cycles following a key event (see Table 10 in
the Register Tables section). This number ranges from
1–31 debounce cycles. Setting bits D7, D6, and D5 set
the FIFO-based interrupt when there are 2–14 key events
stored in the FIFO. Both interrupts can be configured
simultaneously and INTK asserts depending on which
condition is met first. INTK deasserts depending on the
status of bit D5 in the configuration register.
Ports Register (0x04)
The ports register sets the values of PORT2–PORT7 and
the INTK port, when configured, as open-drain GPOs.
Table 2. Key-Switch Mapping
*These columns can be configured as GPOs.
PINCOL0COL1COL2*COL3*COL4*COL5*COL6*COL7*
ROW0KEY 0KEY 8KEY 16KEY 24KEY 32KEY 40KEY 48KEY 56
ROW1KEY 1KEY 9KEY 17KEY 25KEY 33KEY 41KEY 49KEY 57
ROW2KEY 2KEY 10KEY 18KEY 26KEY 34KEY 42KEY 50KEY 58
ROW3KEY 3KEY 11KEY 19KEY 27KEY 35KEY 43KEY 51KEY 59
ROW4KEY 4KEY 12KEY 20KEY 28KEY 36KEY 44KEY 52KEY 60
ROW5KEY 5KEY 13KEY 21KEY 29KEY 37KEY 45KEY 53KEY 61
ROW6KEY 6KEY 14KEY 22KEY 30KEY 38KEY 46KEY 54KEY 62
ROW7KEY 7KEY 15KEY 23KEY 31KEY 39KEY 47KEY 55KEY 63
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
The settings in this register are ignored for ports not con-
figured as GPOs, and a read from this register returns
the values stored in the register (see Table 11 in the
Register Tables section).
Autorepeat Register (0x05)
The MAX7360 autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key
repeat code (0x7E) is entered into the FIFO, and sets the
frequency at which the key-repeat code is entered into
the FIFO thereafter. Bit D7 specifies whether the auto-
repeat function is enabled with 0 denoting autorepeat
disabled, and 1 denoting autorepeat enabled. Bits D0–
D3 specify the autorepeat delay in terms of debounce
cycles ranging from 8–128 debounce cycles (see Table
12 in the Register Tables section). Bits D4, D5, and D6
specify the autorepeat rate or frequency ranging from
4–32 debounce cycles.
When autorepeat is enabled, holding the key pressed
results in a key-repeat event that is denoted by 0x7E. The
key being pressed does not show up again in the FIFO.
Only one autorepeat code is entered into the FIFO,
regardless of the number of keys pressed. The auto-
repeat code continues to be entered in the FIFO at the
frequency set by bits D[4:6] until another key event is
recorded. Following the key-release event, if any keys
are still pressed, the MAX7360 restarts the autorepeat
sequence.
Autosleep Register (0x06)
Autosleep puts the MAX7360 in sleep mode to draw
minimal current. When enabled, the MAX7360 enters
sleep mode if no keys are pressed for the autosleep time
(see Table 13 in the Register Tables section).
Key-Switch Sleep Mode
In sleep mode, the MAX7360 draws minimal current.
Switch-matrix current sources are turned off and pulled
up to VCC. When autosleep is enabled, key-switch
inactivity for a period longer than the autosleep time
puts the part into sleep mode (FIFO data is maintained).
Writing a 1 to D7 in the configuration register, or a key-
press, can take the MAX7360 out of sleep mode. Bit D7
in the configuration register gives the sleep-mode status
and can be read any time. The FIFO data is maintained
while in sleep mode.
Autowake
Keypresses initiate autowake and the MAX7360 goes
into operating mode. Keypresses that autowake the
MAX7360 are not lost. When a key is pressed while the
MAX7360 is in sleep mode, all analog circuitry, including
switch-matrix current sources, turn on in 2ms. The initial
key needs to be pressed for 2ms plus the debounce time
to be stored in the FIFO. Write a 0 to D1 in the configura-
tion register (0x01) to disable autowakeup.
GPIOs
The MAX7360 has eight GPIO ports with LED control
functions. The ports can be used as logic inputs, logic
outputs, or constant-current PWM LED drivers. In addi-
tion, PORT7 and PORT6 can function as a rotary switch
input pair. When in PWM mode, the ports are set up
to start their PWM cycle in 45N phase increments. This
prevents large current spikes on the LED supply voltage
when driving multiple LEDs.
GPIO Global Configuration Register (0x40)
The GPIO global configuration register controls the main
settings for the eight GPIOs (see Table 14 in the Register
Tables section).
Bit D7 enables PORT[7:6] as inputs for a rotary switch.
Bit D5 enables interrupt generation for I2C timeouts. D4
is the main enable/shutdown bit for the GPIOs. D3 func-
tions as a software reset for the GPIO registers (0x40 to
0x5F). Bits D[2:0] set the fade in/out time for the GPIOs
configured as constant-current sinks.
GPIO Control Register (0x41)
The GPIO control register configures each port as either
an input or an output (see Table 15 in the Register Tables
section). All GPIOs allow individual configurations, and
power up as inputs. Enabling rotary switch mode auto-
matically sets D7 and D6 as inputs. The ports consume
additional current if their inputs are left undriven.
GPIO Debounce Configuration Register (0x42)
The GPIO debounce configuration register sets the
amount of time a GPIO must be held for the MAX7360
to register a logic transition (see Table 16 in the Register
Tables section). The GPIO debounce setting is inde-
pendent of the key-switch debounce setting. Five bits
(D[4:0]) set 32 possible debounce times from 9ms up
to 40ms.
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
GPIO Constant-Current Setting Register (0x43)
The GPIO constant-current setting register sets the global
constant-current amount (see Table 17 in the Register
Tables section). Bits D1 and D0 set the global current
values from 5mA up to 20mA.
GPIO Output Mode Register (0x44)
The GPIO output mode register sets an output as either
a constant-current or non-constant-current output for
PORT[7:0] (see Table 18 in the Register Tables section).
Outputs are configured as constant-current outputs by
default to prevent accidental loading of an LED across
an unregulated output. The constant-current circuits
automatically turn off when not in use to reduce current
consumption.
Common PWM Register (0x45)
The common PWM register stores the common constant-
current output PWM duty cycle (see Table 19 in the
Register Tables section). The values stored in this register
translate over to a PWM duty cycle in the same manner
as the individual PWM registers (0x50 to 0x57). Ports can
use their own individual PWM value, or the common PWM
value. Write to this register to change the duty cycle of
several ports at once.
Rotary Switch Configuration Register (0x46)
The rotary switch configuration register stores rotary
switch settings for PORT7 and PORT6 (see Table 20 in
the Register Tables section). D7 determines whether
switch counts or a time delay will trigger an interrupt
if enabled. D[6:4] set the count or time amount to wait
before sending an interrupt. Bits D[3:0] set the debounce
cycle time for the rotary switch inputs. Debounce time
ranges from 0 to 15ms.
I2C Timeout Flag Register (0x48) (Read Only)
The I2C timeout flag register contains a single bit (D0),
which indicates if an I2C timeout has occurred (see Table
21 in the Register Tables section). Read this register to
clear an I2C timeout initiated interrupt.
GPIO Input Register (0x49) (Read Only)
The GPIO input register contains the input data for all of
the GPIOs (see Table 22 in the Register Tables section).
Ports configured as outputs are read as high. There is
one debounce period delay prior to detecting a transition
on the input port. This prevents a false interrupt from
occurring when changing a port from an output to an
input. The GPIO input register reports the state of all
input ports regardless of any interrupt mask settings.
Ports configured as an input have a 2FA internal pullup
to VCC for PORT[5:0] and a 10FA internal pullup to VCC
for PORT[7:6].
Rotary Switch Count Register (0x4A) (Read Only)
The MAX7360 keeps a count of the rotary switch rotations
in two’s compliment format (see Table 23 in the Register
Tables section). The register values wrap around as the
count value switches from a positive to a negative value
and back again. The count resets to zero after an I2C
read to this register.
PORT0–PORT7 Individual PWM Ratio Registers
(0x50 to 0x57)
Each port has an individual PWM ratio register (0x50 to
0x57, see Table 24 in the Register Tables section). Use
values 0x00 to 0xFE in these registers to configure the
number of cycles out of 256 the output sinks current
(LED is on), from 0 cycles to 254 cycles. Use 0xFF to
have an output continuously sink current (always on).
For applications requiring multiple ports to have the
same intensity, program a particular port’s configuration
register (0x58 to 0x5F) to use the common PWM register
(0x45). New PWM settings take place at the beginning of
a PWM cycle, to allow changes from common intensity to
individual intensity with no interruption in the PWM cycle.
PORT0–PORT7 Configuration Registers
(0x58 to 0x5F)
Registers 0x58 to 0x5F set individual configurations for
each port (see Table 25 in the Register Tables section).
Bits D7 and D6 determine the interrupt settings for the
inputs. Interrupts can assert upon detection of a logic
transition, a rising edge, or not at all. D5 sets the port’s
PWM setting to either the common or individual PWM
setting. Bits D[4:2] enable and set the ports’ individual
blink period from 0 to 4096ms. Bits D1 and D0 set a
port’s blink duty cycle.
Fading
Set the fade cycle time in the GPIO global configuration
register (0x40) to a non-zero value to enable fade in/out (see
Table 14 in the Register Tables section). Fade in increases
an LED’s PWM intensity in 16 even steps from zero to its
stored value. Fade out decreases an LED’s PWM intensity in
16 even steps from its current value to zero. Fading occurs
automatically in any of the following scenarios:
1) Change the common PWM register value from any
value to zero to cause all ports using the common
PWM register settings to fade out. No ports using
individual PWM settings are affected.
2) Change the common PWM register value to any
value from zero to cause all ports using the common
PWM register settings to fade in. No ports using indi-
vidual PWM settings are affected.
3) Put the part out of shutdown to cause all ports to fade
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
in automatically cancels that port’s fade and immedi-
ately output at its newly programmed intensity.
4) Put the part into shutdown to cause all ports to fade
out. Changing an individual PWM intensity during
fade out automatically cancels that port’s fade and
immediately turns off.
Blink
Each port has its own blink control settings through reg-
isters 0x58 to 0x5F (see Table 25 in the Register Tables
section). The blink period ranges from 0 (blink disabled)
to 4.096s. Settable blink duty cycles range from 6.25%
to 50%. All blink periods start at the same PWM cycle for
synchronized blinking between multiple ports.
GPIO Port Interrupts (INTI)
Three possible sources generate INTI: I2C timeout,
GPIOs configured as inputs, and the rotary switch
(registers 0x48, 0x49, and 0x4A). Read the respective
data/status registers for each type of interrupt to clear
INTI. Set register 0x46 for rotary switch-based interrupts.
Set registers 0x58 to 0x5F for individual GPI-based inter-
rupts. If multiple sources generate the interrupt, all the
related status registers must be read to clear INTI.
Rotary Switch
The MAX7360 can accept a 2-bit rotary switch inputs on
PORT6 and PORT7. Rotation of the switch in a clockwise
direction increments the count. Enable rotary switch
mode from the GPIO global configuration register (0x40).
Several settings for PORT6 and PORT7 occur during
rotary switch mode:
1) Each port has a 10FA pullup to VCC.
2) Register 0x46 sets the debounce time.
3) A debounced rising edge on PORT6 while PORT7 is
high decreases the count.
4) A debounced rising edge on PORT6 while PORT7 is
low increases the count.
For more details, see Figure 1.
Serial Interface
Figure 2 shows the 2-wire serial interface timing details.
Serial Addressing
The MAX7360 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial-data line (SDA) and
a serial-clock line (SCL) to achieve bidirectional com-
munication between master(s) and slave(s). A master
(typically a microcontroller) initiates all data transfers to
and from the MAX7360 and generates the SCL clock that
synchronizes the data transfer.
The MAX7360’s SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kI,
Figure 1. Rotary Switch Input Signal Timing
SDA
SCL
tHD, STA
tLOW
tHIGHtF
tSU, DATtSU, STA
tSU, STO
tBUF
tHD, STA
tHD, DAT
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED
START CONDITION
tF, TX
PORT7
PORT6
PORT7
PORT6
INCREMENT
DECREMENT
ROTARY SWITCH
DEBOUNCE
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
is required on SDA. The MAX7360’s SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the MAX7360
7-bit slave address plus R/W bit, a register address byte,
one or more data bytes, and finally, a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 4). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 5), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and
the recipient pulls down SDA during the acknowledge
clock pulse; therefore, the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7360, the MAX7360 generates
the acknowledge bit because the MAX7360 is the recipi-
ent. When the MAX7360 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
Figure 3. START and STOP Conditions
Table 3. 2-Wire Interface Address Map
PIN AD0DEVICE ADDRESSA6A5A4A3A2A1A0
GND0111000R/W
VCC0111010R/W
SDA0111100R/W
SCL0111110R/W
SDA
SCL
START
CONDITION
STOP
CONDITION P
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
Figure 5. Acknowledge
Figure 6. Slave Address
Slave Addresses
The MAX7360 has a 7-bit long slave address (Figure
6). The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command.
The first 4 bits (MSBs) of the MAX7360 slave address
are always 0111. Slave address bits A3, A2, and A1
correspond, by the matrix in Table 3, to the states of the
device address input AD0, and A0 corresponds to the
R/W bit. The AD0 input can be connected to any of four
signals (GND, VCC, SDA, or SCL), giving four possible
slave address pairs and allowing up to four MAX7360
dynamic signals, care must be taken to ensure that AD0
transitions no sooner than the signals on SDA and SCL.
The MAX7360 monitors the bus continuously, waiting for a
START condition, followed by its slave address. When the
MAX7360 recognizes its slave address, it acknowledges
and is then ready for continued communication.
Bus Timeout
The MAX7360 features a 20ms minimum bus timeout
on the 2-wire serial interface, largely to prevent the
MAX7360 from holding the SDA I/O low during a read
transaction should the SCL lock up for any reason before
Figure 7. Command Byte Received
Figure 8. Command and Single Data Byte Received
SCL
SDA
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
RECEIVER2 8 9
SDA
SCL11A3A2A11
MSBLSB
ACKR/WAAP0SLAVE ADDRESSCOMMAND BYTED6D5D4D3D2D1D0COMMAND BYTE IS STORED ON RECEIPT OF
ACKNOWLEDGE CONDITION
ACKNOWLEDGE FROM MAX7360
ACKNOWLEDGE FROM MAX7360
R/WAAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
1 BYTE
AUTOINCREMENT
COMMAND BYTE ADDRESSD6D5D4D3D2D1D0D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7360ACKNOWLEDGE FROM MAX7360
ACKNOWLEDGE FROM MAX7360
R/W
2C-Interfaced Key-Switch Controller and LED Driver/GPIOs with Integrated ESD Protection
MAX7360
transaction, either read or write, if SCL low exceeds
20ms. After a bus timeout, the MAX7360 waits for a valid
START condition before responding to a consecutive
transmission. This feature can be enabled or disabled
under user control by writing to the configuration register
(Table 8 in the Register Tables section).
Message Format for Writing
the Key-Scan Controller
A write to the MAX7360 comprises the transmission of the
slave address with the R/W bit set to zero, followed by at
least 1 byte of information. The first byte of information
is the command byte. The command byte determines
which register of the MAX7360 is to be written by the next
byte, if received. If a STOP condition is detected after the
command byte is received, the MAX7360 takes no further
action (Figure 7) beyond storing the command byte.
Any bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
MAX7360 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP condi-
tion is detected, these bytes are generally stored in subse-
quent MAX7360 internal registers, because the command
byte address generally autoincrements (Table 4).
Message Format for Reading
the Key-Scan Controller
The MAX7360 is read using the internally stored com-
mand byte as an address pointer, the same way the
stored command byte is used as an address pointer
for a write. The pointer generally autoincrements after
write (Table 4). Thus, a read is initiated by first config-
uring the MAX7360’s command byte by performing a
write (Figure 7). The master can now read n consecutive
bytes from the MAX7360, with the first data byte being
read from the register addressed by the initialized com-
mand byte. When performing read-after-write verifica-
tion, remember to reset the command byte’s address,
because the stored command byte address is generally
autoincremented after the write (Figure 9, Table 4).
Operation with Multiple Masters
When the MAX7360 is operated on a 2-wire interface
with multiple masters, a master reading the MAX7360
uses a repeated start between the write that sets the
MAX7360’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is pos-
sible for master 2 to take over the bus after master 1 has
set up the MAX7360’s address pointer, but before mas-
ter 1 has read the data. If master 2 subsequently resets
the MAX7360’s address pointer, master 1’s read can be
from an unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX7360 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX7360
generally increments after each data byte is written or
read (Table 4). Autoincrement only works when doing a
multiburst read or write.
Applications Information
Reset from I2C
After a catastrophic event such as ESD discharge or
microcontroller reset, use bit D7 of the configuration
register (0x01) as a software reset for the key-switch
state (the key-switch register values and FIFO remain
unaffected). Use bit D4 of the GPIO global configura-
tion register (0x40) as a software reset for the GPIOs.
Figure 9. N Data Bytes Received
Table 4. Autoincrement Rules
REGISTER
FUNCTION
ADDRESS
CODE (hex)
AUTOINCREMENT
ADDRESS (hex)
Keys FIFO0x000x00
Autoshutdown0x060x00
All other key switch0x01 to 0x05Addr + 0x01
All other GPIO0x40 to 0x5FAddr + 0x01AAAP0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
N BYTES
AUTOINCREMENT
COMMAND BYTE ADDRESSD6D5D4D3D2D1D0D1D0D3D2D5D4D7D6
ACKNOWLEDGE FROM MAX7360ACKNOWLEDGE FROM MAX7360
ACKNOWLEDGE FROM MAX7360
R/W
