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MAX7327AATG+MAXIMN/a6012avaiI²C Port Expander with 12 Push-Pull Outputs and 4 Open-Drain I/Os
MAX7327AATG+T |MAX7327AATGTMAXN/a1850avaiI²C Port Expander with 12 Push-Pull Outputs and 4 Open-Drain I/Os


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MAX7327AATG+-MAX7327AATG+T
I²C Port Expander with 12 Push-Pull Outputs and 4 Open-Drain I/Os
Typical Application Circuit and Functional Diagram appear
at end of data sheet.

Pin Configurations continued at end of data sheet.●Cell Phones●SAN/NAS●Servers●Notebooks●Satellite Radio
General Description

The MAX7327, a 2-wire serial-interfaced peripheral,
features 12 push-pull outputs and four configurable open-
drain I/O ports with selectable internal pullups and tran-
sition detection. Ports are overvoltage protected to +6V,
independent of supply voltage.
The four I/O ports configured as inputs are continuously
monitored for state changes (transition detection). State
changes are indicated by the open-drain, +6V-tolerant
INT output. The interrupt is latched, detecting transient
changes. When the MAX7327 is subsequently accessed
through the serial interface, any pending interrupt is
cleared. The 12 push-pull and the four open-drain outputs
are rated to sink 20mA, and are capable of driving LEDs.
The RST input clears the serial interface, terminating any
I2C communication to or from the MAX7327.
The MAX7327 uses two address inputs with four-level
logic to allow 16 I2C slave addresses. The slave address
also determines the power-up logic state for the I/O ports,
and enables or disables internal 40kΩ pullups in groups
of two ports.
The MAX7327 is one device in a family of pin-compatible
port expanders with a choice of input ports, open-drain I/O
ports, and push-pull output ports (see Table 1).
The MAX7327 is available in the 24-pin QSOP and
TQFN packages, and is specified over the -40°C to
+125°C automotive temperature range.
Applications
Features
●400kHz I2C Serial Interface●+1.71V to +5.5V Operating Voltage●12 Push-Pull Output Ports, Rated at 20mA Sink
Current●4 Open-Drain I/O Ports, Rated at 20mA Sink Current●I/O Ports are Overvoltage Protected to +6V●Selectable I/O Port Power-Up Default Logic States●Transient Changes are Latched, Allowing Detection
Between Read Operations●INT Output Alerts Changes on Inputs●AD0 and AD2 Inputs Select from 16 Slave Addresses●Low 0.6µA (typ) Standby Current●-40°C to +125°C Temperature Range
+Denotes a lead(Pb)-free/RoHS-compliant package.
**EP = Exposed pad.
PARTINPUTSINTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-PULL
OUTPUTS

MAX73248Yes—8
MAX7325Up to 8—Up to 88
MAX73264Yes—12
MAX7327Up to 4—Up to 412
PARTTEMP RANGEPIN-PACKAGE

MAX7327AEG+-40°C to +125°C24 QSOP
MAX7327ATG+-40°C to +125°C24 TQFN-EP*
(4mm x 4mm)
MAX7327AATG+-40°C to +125°C24 TQFN-EP*
(3.5mm x 3.5mm)
TQFN (4mm x 4mm)

TOP VIEW
MAX7327234561716151413
SCL
SDA
INT
AD2P3P4P5
AD0O15O13O12O11
RST
O10
GND
O14
EXPOSED PADDLE
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
Selector Guide
Ordering Information
Pin Conigurations
EVALUATION KIT AVAILABLE
(All voltages referenced to GND.)
Supply Voltage V+ ...................................................-0.3V to +6V
SCL, SDA, AD0, AD2, RST, INT, P2–P5 ...............-0.3V to +6V
O0, O1, O6–O15 ...........................................-0.3V to V+ + 0.3V
O0, O1, O6–O15 Output Current ....................................±25mA
P2–P5 Sink Current ..........................................................25mA
SDA Sink Current ..............................................................10mA
INT Sink Current ................................................................10mA
Total V+ Current ................................................................50mA
Total GND Current ...........................................................100mA
Continuous Power Dissipation (TA = +70°C)24-Pin QSOP (derate 9.5mW/°C over +70°C) .........761.9mW24-Pin TQFN (derate 20.8mW/°C over +70°C) ......1666.7mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Operating Supply VoltageV+TA = -40°C to +125°C1.715.50V
Power-On Reset VoltageVPORV+ falling1.6V
Standby Current
(Interface Idle)ISTBSCL and SDA and other
digital inputs at V+
TA = -40°C to
+125°C0.61.9µA
Supply Current
(Interface Running)I+fSCL = 400kHz; other
digital inputs at V+
TA = -40°C to
+125°C2355µA
Input High-Voltage
SDA, SCL, AD0, AD2, RST, P2–P5VIHV+ < 1.8V0.8 x V+VV+ ≥ 1.8 V0.7 x V+
Input Low-Voltage
SDA, SCL, AD0, AD2, RST, P2–P5VILV+ < 1.8V0.2 x V+VV+ ≥ 1.8 V0.3 x V+
Input Leakage Current
SDA, SCL, AD0, AD2, RST, P2–P5IIH, IILSDA, SCL, AD0, AD2, RST, P0–P7 at
V+ or GND, internal pullup disabled-0.2+0.2µA
Input Capacitance
SDA, SCL, AD0, AD2, RST, P2–P510pF
Output Low Voltage
O8–O15, P0, P7VOL
V+ = 1.71V, ISINK = 5mA (QSOP)90180
V+ = 1.71V, ISINK = 5mA (TQFN)90230
V+ = 2.5V, ISINK = 10mA (QSOP)110210
V+ = 2.5V, ISINK = 10mA (TQFN)110260
V+ = 3.3V, ISINK = 15mA (QSOP)130230
V+ = 3.3V, ISINK = 15mA (TQFN)130280
V+ = 5V, ISINK = 20mA (QSOP)140250
V+ = 5V, ISINK = 20mA (TQFN)140300
Output High Voltage
O0, O1, O6–O15, P2–P5VOH
V+ = +1.71V, ISOURCE = 2mAV+ - 250V+ - 30V+ = +2.5V, ISOURCE = 5mAV+ - 360V+ - 70
V+ = +3.3V, ISOURCE = 5mAV+ - 260V+ - 100
V+ = +5V, ISOURCE = 10mAV+ - 360V+ - 120
Output Low-Voltage SDAVOLSDAISINK = 6mA250mV
Output Low-Voltage INTVOLINTISINK = 5mA130250mV
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
DC Electrical Characteristics

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2:
A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 3:
Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3 x V+ and 0.7 x V+ with ISINK ≤ 6mA.

(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Serial-Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP
and a START Condition tBUF1.3µs
Hold Time (Repeated) START
ConditiontHD, STA0.6µs
Repeated START Condition
Setup TimetSU, STA0.6µs
STOP Condition Setup TimetSU, STO0.6µs
Data Hold TimetHD, DAT(Note 2)0.9µs
Data Setup TimetSU, DAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Notes 3, 4)20 +
0.1Cb300ns
Fall Time of Both SDA and SCL
Signals, ReceivingtF(Notes 3, 4)20 +
0.1Cb300ns
Fall Time of SDA TransmittingtF,TX(Notes 3, 4)20 +
0.1Cb250ns
Pulse Width of Spike SuppressedtSP(Note 5)50ns
Capacitive Load for Each Bus
LineCb(Note 3)400pF
RST Pulse WidthtW500ns
RST Rising to START Condition
Setup TimetRST1µs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Port Output Data ValidtPPVCL ≤ 100pF4µs
Port Input Setup TimetPSUCL ≤ 100pF0µs
Port Input Hold TimetPHCL ≤ 100pF4µs
INT Input Data Valid TimetIVCL ≤ 100pF4µs
INT Reset Delay Time from STOPtIPCL ≤ 100pF4µs
INT Reset Delay Time from
AcknowledgetIRCL ≤ 100pF4µs
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
Timing Characteristics
Port and Interrupt INT Timing Characteristics
(TA = +25°C, unless otherwise noted.)
PINNAMEFUNCTIONQSOPTQFN
22INTActive-Low Interrupt Output. INT is an open-drain output.23RSTActive-Low Reset Input. Drive RST low to clear the 2-wire interface.
3, 2124, 18AD2, AD0Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and AD2
to either GND, V+, SCL, or SDA to give four logic combinations (see Tables 2 and 3).
4, 5, 10,
11, 13–20
1, 2, 7, 8,
O0, O1,
O6–O15Output Ports. O0, O1, O6–O15 are push-pull outputs rated at 20mA.
6–93–6 P2–P5P2–P5 Open-Drain I/Os9GNDGround19SCLI2C-Compatible Serial Clock Input20SDAI2C-Compatible Serial Data I/O21V+Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor.
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE

TEMPERATURE (°C)
OUTPUT VOLTAGE HIGH (V)
MAX7327 toc04
V+ = +3.3V
ISOURCE = 5mA
V+ = +5.0V
ISOURCE = 10mA
V+ = +2.5V ISOURCE = 5mA
V+ = +1.71V ISOURCE = 2mA
OUTPUT VOLTAGE LOW
vs. TEMPERATURE

TEMPERATURE (°C)
OUTPUT VOLTAGE LOW (V)
MAX7327 toc03
V+ = +3.3V
ISINK = 15mA
V+ = +5.0V
ISINK = 20mA
V+ = +2.5V
ISINK = 10mA
V+ = +1.71V
ISINK = 5mA
V+ = +1.62V
ISINK = 4mA
SUPPLY CURRENT
vs. TEMPERATURE

TEMPERATURE (°C)
SUPPLY CURRENT (A)
MAX7327 toc02
V+ = +3.3V
V+ = +5.0V
V+ = +2.5V
V+ = +1.71V
fSCL = 400kHz
STANDBY CURRENT
vs. TEMPERATURE

TEMPERATURE (°C)
STANDBY CURRENT (A)
MAX7327 toc01
V+ = +3.3V
V+ = +5.0V
V+ = +2.5V
V+ = +1.71V
fSCL = 0kHz
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
Pin Description
Typical Operating Characteristics
Detailed Description
MAX7319–MAX7329 Family Comparison

The MAX7324–MAX7327 family consists of four pin-
compatible, 16-port expanders that integrate the
functions of the MAX7320 and one of either the MAX7319,
MAX7321, MAX7322, or MAX7323.
Functional Overview

The MAX7327 is a general-purpose port expander
operating from a +1.71V to +5.5V supply that provides
12 push-pull output ports with a 20mA sink, 10mA
source drive capability, and four open-drain I/O ports
with a 20mA sink capability. The four open-drain out-
puts are overvoltage protected to +6V.
The MAX7327 is set to two of 32 I2C slave addresses
(see Tables 2 and 3) using address inputs AD2 and AD0,
and is accessed over an I2C serial interface up to 400kHz.
Eight push-pull outputs use a different slave address from
the other four push-pull outputs and the open-drain I/Os.
The eight push-pull outputs (O8–O15) use the 101xxxx
addresses while the four outputs (O0, O1, O6, and O7)
and the open-drain I/Os (P2–P5) use addresses with
110xxxx. The RST input clears the serial interface in case
of a bus lockup, terminating any serial transaction to or
from the MAX7327.
Any of the four open-drain ports can be configured as a
logic input by setting the port output logic-high (logic-high
for an open-drain output is high impedance). When the
MAX7327 is read through the serial interface, the actual
logic levels at the ports are read back.
Table 1. MAX7319–MAX7329 Family Comparison
PART
I2C
SLAVE
ADDRESS
INPUTS
INPUT
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION
16-PORT EXPANDERS

MAX7324
101xxxx
and
110xxxxYes—8
8 inputs and 8 push-pull outputs version:
8 input ports with programmable latching transition
detection interrupt and selectable pullups.
8 push-pull outputs with selectable default logic
levels.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even if only for
a transient) since the ports were last read.
MAX7325Up to 8—Up to 88
8 I/O and 8 push-pull outputs version:
8 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
8 push-pull outputs with selectable default logic
levels.
Open-drain outputs can level shift the logic-high state
to a higher or lower voltage than V+ using external
pullup resistors, but pullups draw current when output
is low. Any open-drain port can be used as an input
by setting the open-drain output to logic-high.
Transition flags identify which open-drain port inputs
have changed (even if only for a transient) since the
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
Table 1. MAX7319–MAX7329 Family Comparison (continued)
PART
I2C
SLAVE
ADDRESS
INPUTS
INPUT
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION

MAX7326
101xxxx
and
110xxxxYes—12
4 input-only, 12 push-pull output versions:
4 input ports with programmable latching transition
detection interrupt and selectable pullups.
12 push-pull outputs with selectable default logic
levels.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even if only for
a transient) since the ports were last read.
MAX7327Up to 4—Up to 412
4 I/O, 12 push-pull output versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
12 push-pull outputs with selectable default logic
levels.
Open-drain outputs can level shift the logic-high state
to a higher or lower voltage than V+ using external
pullup resistors, but pullups draw current when output
is low. Any open-drain port can be used as an input
by setting the open-drain output to logic-high.
Transition flags identify which open-drain port inputs
have changed (even if only for a transient) since the
ports were last read.
8-PORT EXPANDERS

MAX7319110xxxx8Yes——
Input-only versions:
8 input ports with programmable latching transition
detection interrupt and selectable pullups.
MAX7320101xxxx———8
Output-only versions:
8 push-pull outputs with selectable power-up default
levels.
MAX7321110xxxxUp to 8—Up to 8—
I/O versions:
8 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
MAX7322110xxxx4Yes—4
4 input-only, 4 output-only versions:
4 input ports with programmable latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
The four open-drain ports offer latching transition
detection functionality when used as inputs. All input ports
are continuously monitored for changes. An input change
sets 1 of 4 flag bits that identify the changed input(s). All
flags are cleared upon a subsequent read or write trans-
action to the MAX7327.
A latching interrupt output (INT) automatically flags data
changes on any of the I/O ports used as inputs through
an interrupt mask register. Data changes on any input
port forces INT to a logic-low. Interrupt output INT is
deasserted when the MAX7327 is next accessed through
the serial interface.
Internal pullup resistors to V+ are selected by the address
select inputs, AD0 and AD2. Pullups are enabled on the
input ports in groups of two (see Table 2). Use the slave
address selection to ensure that I/O ports used as inputs
are logic-high on power-up. I/O ports with internal pullups
enabled default to a logic-high output state. I/O ports
with internal pullups disabled default to a logic-low output
state.
Output port power-up logic levels are selected by the
address select inputs (AD0 and AD2). Ports default to
logic-high or logic-low on power-up in groups of two (see
Tables 2 and 3).
Initial Power-Up

On power-up, the default states of the 12 push-pull
output ports and the four open-drain I/O ports are set
according to the I2C slave address selection inputs,
AD0 and AD2 (see Tables 2 and 3). For I/O ports
used as inputs, ensure that the default states are
logic-high; therefore, the I/O ports power up in the
high-impedance state. All I/O ports configured with pullups
enabled also have a logic-high default state. On power-
up, the transition detection logic is reset, and INT is
deasserted. The transition flags are cleared, indicating no
data changes.
Power-On Reset (POR)

The MAX7327 contains an integral POR circuit that
ensures all registers are reset to a known state on
power-up. When V+ rises above VPOR (1.6V max), the
POR circuit releases the registers and 2-wire interface
for normal operation. When V+ drops to less than VPOR,
the MAX7327 resets all register contents to the POR
defaults (Tables 2 and 3).
RST Input

The active-low reset input (RST) operates as a hardware
reset that voids any I2C transaction involving the MAX7327,
forcing the MAX7327 into the I2C STOP condition. A
reset does not affect the interrupt output (INT).
Standby Mode

When the serial interface is idle, the MAX7327
automatically enters standby mode, drawing minimal
supply current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7327
slave address and select which inputs have pullup
resistors. Pullups are enabled on the input ports in groups
of two (see Table 2).
The MAX7327 slave address is determined on each I2C
transmission, regardless of whether the transmission
is actually addressing the MAX7327. The MAX7327
distinguishes whether address inputs AD0 and AD2 are
connected to SDA or SCL instead of fixed-logic levels V+
Table 1. MAX7319–MAX7329 Family Comparison (continued)
PART
I2C
SLAVE
ADDRESS
INPUTS
INPUT
INTERRUPT
MASK
OPEN-
DRAIN
OUTPUTS
PUSH-
PULL
OUTPUTS
CONFIGURATION

MAX7323110xxxxUp to 4—Up to 44
4 I/O, 4 output-only versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7328
MAX7329
0100xxx
0111xxxUp to 8—Up to 8—
PCF8574-, PCF8574A-compatible versions:
8 open-drain I/O ports with nonlatching transition
detection interrupt and pullups on all ports.
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
address can be configured dynamically in the application
without cycling the device supply.
On initial power-up, the MAX7327 cannot decode the
address inputs AD0 and AD2 fully until the first I2C trans-
mission. AD0 and AD2 initially appear to be connected
to V+ or GND. This is important because the address
selection is used to determine the power-up default states
of the output ports, I/O port initial logic state, and whether
pullups are enabled. At power-up, the I2C SDA and SCL
bus interface lines are high impedance at the I/O pins
of every device (master or slave) connected to the bus,
including the MAX7327. This is guaranteed as part of the
I2C specification. Therefore, when address inputs AD0
and AD2 are connected to SDA or SCL during power-up,
they appear to be connected to V+. The pullup selection
logic uses AD0 to select whether pullups are enabled
for ports P2 and P3, and uses AD2 to select whether
pullups are enabled for ports P4 and P5. The rule is that
a logic-high, SDA, or SCL connection selects the pullups
and sets the logic state to high. A logic-low deselects the
pullups and sets the default logic state to low. The pullup
configuration is correct on power-up for a standard I2C
configuration, where SDA or SCL are pulled up to V+ by
the external I2C pullup resistors.
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true; for example, in
applications in which there is legitimate bus activity during
power-up. If SDA and SCL are terminated with pullup
resistors to a different supply voltage to the MAX7327’s
supply voltage, and if that pullup supply rises later than
the MAX7327’s supply, then SDA or SCL may appear at
power-up to be connected to GND. In such applications,
use the four address combinations that are selected by
connecting address inputs AD0 and AD2 to V+ or GND
(shown in bold in Tables 2 and 3). These selections are
guaranteed to be correct at power-up, independent of
SDA and SCL behavior. If one of the other 12 address
combinations is used, an unexpected combination of
pullups might be asserted until the first I2C transmission
(to any device, not necessarily the MAX7327) is put on
the bus.
Table 2. MAX7327 Address Map for Outputs O0, O1, O6, O7, and Ports P2–P5
PIN
CONNECTIONDEVICE ADDRESSPORTS POWER-UP DEFAULT40kΩ INPUT PULLUPS ENABLED
AD2AD0A6A5A4A3A2A1A0O7O6P5P4P3P2O1O0O7O6P5P4P3P2O1O0

SCLGND110000011110000
Pullups are not enabled for push-pull outputsY——
Pullups are not enabled for push-pull outputs
SCLV+110000111111111YYYY
SCLSCL110001011111111YYYY
SCLSDA110001111111111YYYY
SDAGND110010011110000YY——
SDAV+110010111111111YYYY
SDASCL110011011111111YYYY
SDASDA110011111111111YYYY
GNDGND110100000000000————
GND
V+110100100001111——YY
GNDSCL110101000001111——YY
GNDSDA110101100001111——YYGND110110011110000YY——V+110110111111111YYYYSCL110111011111111YYYYSDA110111111111111YYYY
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
I/O Port Inputs
I/O port inputs switch at CMOS logic levels as determined
by the expander’s supply voltage, and are overvoltage
tolerant to +6V, independent of the expander’s supply
voltage.
I/O Port Input Transition Detection

All I/O ports configured as inputs are monitored for
changes since the expander was last accessed through
the serial interface. The state of the ports is stored in
an internal “snapshot” register for transition monitoring.
The snapshot is continuously compared with the actual
input conditions, and if a change is detected for any port
input, INT is asserted to signal a state change. The input
ports are sampled (internally latched into the snapshot
register) and the old transition flags cleared during the I2C
acknowledge of every MAX7327 read and write access.
The previous port-transition flags are read through the
serial interface as the second byte of a 2-byte read
sequence.
A long read sequence (more than 2 bytes) can be used
to poll the expander continuously without the overhead
of resending the slave address. If more than 2 bytes are
read from the expander, the expander repeatedly returns
the 2 bytes of input port data followed by the transition
flags. The inputs are repeatedly resampled and the
transition flags repeatedly reset for each pair of bytes
read. All changes that occur during a long read sequence
are detected and reported.
The INT output is not reasserted during a read sequence
to avoid recursive reentry into an interrupt service
routine. Instead, if a data change occurs that would
normally cause the INT output to be set, the INT assertion
is delayed until the STOP condition. INT is not reassert-
ed upon a STOP condition if the changed input data is
read before the STOP occurs. The INT logic ensures
that unnecessary interrupts are not asserted, yet data
changes are detected and reported no matter when the
change occurs.
Table 3. MAX7327 Address Map for Outputs O8–O15
PIN
CONNECTIONDEVICE ADDRESSOUTPUTS POWER-UP DEFAULT
AD2AD0A6A5A4A3A2A1A0O15O14O13O12O11O10O9O8

SCLGND101000011110000
SCLV+101000111111111
SCLSCL101001011111111
SCLSDA101001111111111
SDAGND101010011110000
SDAV+101010111111111
SDASCL101011011111111
SDASDA101011111111111
GNDGND101100000000000
GNDV+101100100001111
GNDSCL101101000001111

GNDSDA101101100001111GND101110011110000V+101110111111111SCL101111011111111SDA101111111111111
MAX7327I2C Port Expander with 12 Push-Pull
Outputs and 4 Open-Drain I/Os
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