MAX7306ALB+T Fast Delivery |IC PHOENIX CO.,LIMITED

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MAX7306ALB+T
SMBus/I²C Interfaced 4-Port, Level-Translating GPIOs and LED Drivers
General Description
The MAX7306/MAX7307 I2C-/SMBus™-compatible, seri-
al-interfaced peripherals feature four level-translating
I/Os and operate from a 1.62V to 3.6V power supply.
The MAX7307 features a port supply (VLA) that allows
level translation on I/O ports to operate from a separate
power supply from 1.4V to 5.5V. The MAX7306 features
an address select input (AD0) to allow up to four unique
slave addresses.
The MAX7306/MAX7307 ports P2, P3, and P4 can be
configured as inputs, push-pull outputs, and open-drain
outputs. Port P1 can be configured as a general-pur-
pose input, open-drain output, or an open-drain INTout-
put. Ports P2 and P3 can be configured as OSCIN and
OSCOUT, respectively. The MAX7306/MAX7307 include
an internal oscillator for PWM, blink, and key debounce,
or to cascade multiple MAX7306/MAX7307s. The exter-
nal clock can be used to set a specific PWM and blink
timing. The RSTinput asynchronously clears the 2-wire
interface and terminates a bus lockup involving the
MAX7306/MAX7307.
All ports configured as output feature 33-step PWM,
allowing any output to be set from fully off, 1/32 to 31/32
duty cycle, to fully on. All output ports also feature LED
blink control, allowing blink periods of 1/8 second, 1/4
second, 1/2 second, 1, 2, 4, or 8 seconds. Any port can
blink during this period with a 1/16 to 15/16 duty cycle.
The MAX7306/MAX7307 are specified over the -40°C to
+125°C temperature range and are available in 10-pin
µDFN (2mm x 2mm) and 10-pin µMAX®packages.
Applications
Cell PhonesLCD/Keypad Backlights
System I/O PortsLED Status Indicators
Features1.4V to 5.5V I/O Level Translation Port Supply (VLA)1.62V to 3.6V Power SupplyFour Individually Configurable GPIO Ports
P1 = Open-Drain I/OP2, P3, P4 = Push-Pull or Open-Drain I/OIndividual 33-Step PWM Intensity ControlBlink Controls with 15 Steps on Outputs1kHz PWM Period Provides Flicker-Free LEDIntensity Control25mA (max) Port Output Sink Current (100mAmax Ground Current)Inputs Overvoltage Protected Up to 5.5V (VLA)Transition Detection with Optional Interrupt OutputOptional Input DebouncingRSTInput Clears Serial Interface, Can Restore
Power-Up Default State, and Synchronizes BlinkTimingOscillator Input and Output Enables Cascading
Multiple DevicesLow 0.75µA (typ) Standby Current
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Ordering Information
19-0836; Rev 1; 8/10
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
EVALUATION KIT
AVAILABLE
SMBus is a trademark of Intel Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
PARTTOP MARKPIN-PACKAGE
MAX7306ALB+AAL10 µDFN (2mm x 2mm)
Note:All devices are specified over the -40°C to +125°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
SDA
GND
+1.8V
VDDVLA
P2/OSCIN
P3/OSCOUT
+4.5V
MAX7307
SCL
RST
INT
SDA
SCL
RST
P1/INT
AD0
SDA
GND
+2.5V
VDD
P2/OSCIN
P3/OSCOUT
MAX7306
SCL
RST
INT
SDA
SCL
RST
P1/INT
Typical Operating Circuit
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (MAX7306)
(VDD= 1.62V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD= 3.3V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VDD..........................................................................-0.3V to +4V
VLA, SCL, SDA, AD0, and RST.................................-0.3V to +6V
P1/INT, P2/OSCIN, P3/OSCOUT, and P4
MAX7306................................................-0.3V to (VDD+ 0.3V)
MAX7307.................................................-0.3V to (VLA+ 0.3V)
P1/INT, P2/OSCIN, P3/OSCOUT, and P4 Sink Current ......25mA
P2/OSCIN, P3/OSCOUT, and P4 Source Current ..............10mA
SDA Sink Current ...............................................................10mA
VDDCurrent .......................................................................10mA
VLACurrent (MAX7307)......................................................30mA
GND Current ....................................................................100mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µDFN (derate 5.0mW/°C over +70°C)..............402mW
10-Pin µMAX (derate 10.3mW/°C over +70°C)............825mW
Operating Temperature Range.........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Supply VoltageVDD1.623.60V
Power-On Reset VoltageVPORVDD rising1.01.31.6V
Power-On Reset HysteresisVPORHYST10131300mV
ISTB
Internal oscillator disabled; SCL,
SDA, digital inputs at VDD or
GND; P1–P4 (as inputs) at VDD or
GND
Standby Current (Interface Idle)
IOSC
Internal oscillator enabled; SCL,
SDA, digital inputs at VDD or
GND; P1–P4 (as inputs) at VDD or
GND25up p l y C ur r ent ( Inter face Runni ng ) ISUPfS C L = 400kH z; other d i g i tal i np uts
at VDD or GND3340µA
Input High Voltage SDA, SCL, AD0VIH0.7 x VDDV
Input Low Voltage SDA, SCL, AD0VIL0.3 x VDDV
Input High Voltage RST, P1–P4VIHP0.7 x VDDV
Input Low Voltage RST, P1–P4VILP0.3 x VDDV
Inp ut Leakag e C ur r ent S D A, S C L, AD 0IIH, IILVDD or GND-1+1µA
Input Leakage Current RST, P1–P4IIHP, IILPVDD or GND-1+1µA
Input Capacitance SDA, SCL, AD0, P1–P48pF
VDD = 1.62V, ISINK = 3mA0.060.11
VDD = 2.5V, ISINK = 16mA0.190.4Output Low Voltage P1–P4VOL
VDD = 3.3V, ISINK = 20mA0.20.4
VDD = 1.62V, ISOURCE = 0.5mA1.551.6
VDD ≥ 2.5V, ISOURCE = 5mAV D D - 0.32.3Output High Voltage P2, P3, and P4VOH
VDD ≥ 3.3V, ISOURCE = 8mAV D D - 0.43.1
Output Low Voltage SDAVOLSDAISINK = 6mA0.3V
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
ELECTRICAL CHARACTERISTICS (MAX7307)
(VDD= 1.62V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V, TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Supply VoltageVDD1.623.60V
Port Logic Supply VoltageVLA1.405.50V
Power-On Reset VoltageVPORVDD rising1.01.31.6V
Power-On Reset HysteresisVPORHYST10131300V
ISTB
Inter nal osci l l ator d i sab l ed ; S C L,D A, d i g i tal i np uts at V D D or G N D ;1–P 4 ( as i np uts) at V L A or G N D
Standby Current (Interface Idle)
IOSC
Inter nal osci l l ator enab l ed ; S C L,D A, d i g i tal i np uts at V D D or G N D ;1–P 4 ( as i np uts) at V L A or G N D 25up p l y C ur r ent ( Inter face Runni ng ) ISUPfSCL = 400kHz; other digital
inputs at VLA or GND3340µA
Port Supply Current (VLA)IVLAPort (configured as inputs) at VLA
or GND0.055µA
Input High Voltage SDA, SCL, RSTVIH0.7 x VDDV
Input Low Voltage SDA, SCL, RSTVIL0.3 x VDDV
Input is VLA referred0.7 x VLAInput High Voltage P1–P4VIHPAInput is VDD referred0.7 x VDDV
Input is VLA referred0.3 x VLAInput Low Voltage P1–P4VILPAInput is VDD referred0.3 x VDDV
Inp ut Leakag e C ur r ent S D A, S C L, AD 0, RSTIIH, IILVDD or GND-1+1µA
Input Leakage Current P1–P4IIHP, IILPVLA or GND-1+1µA
Input Capacitance SDA, SCL, AD0, RST,
P1–P480.11pF
VDD = 1.62V, ISINK = 3mA0.060.11
VDD = 2.5V, ISINK = 16mA0.190.4Output Low Voltage P1–P4VOL
VDD = 3.3V, ISINK = 20mA0.20.4
VLA = 1.62V, ISOURCE = 0.5mA1.31.4
VLA = 2.5V, ISOURCE = 5mAV LA - 0.32.3Output High Voltage P2, P3, P4VOH
VLA = 3.3V, ISOURCE = 8mAV LA - 0.43.1
Output Low Voltage SDAVOLSDAISINK = 6mA0.3V
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS
(VDD= 1.62V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V (MAX7307 only), TA=
+25°C.) (Note 1) (See Figures 14, 15, and 16)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
fCLK = internal oscillator32kHzOscillator FrequencyfCLKfCLK = external input1MHz
Port Output Data Valid High TimetPPVHCL ≤ 100pF4µs
Port Output Data Valid Low Time (Internal or
External Oscillator Running)tPPVL1CL ≤ 100pF (Note 2)1 / fCLKµs
Port Output Data Valid Low Time (Oscillator Not
Running)tPPVL2CL ≤ 100pF40µs
Port Input Setup TimetPSUCL = 100pF0µs
Port Input Hold TimetPHCL = 100pF4µs
INT Input Data Valid TimetIVCL = 100pF4µs
INT Reset Delay Time from AcknowledgetIRCL = 100pF4µs
RST Pulse WidthtW500ns
RST Rising to START Condition Setup TimetRST900ns
TIMING CHARACTERISTICS
(VDD= 1.62V to 3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VDD= 3.3V, VLA= 3.3V (MAX7307 only), TA=
+25°C.) (Note 1) (See Figure 8)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Serial-Clock FrequencyfSCL400kHz
Bus TimeouttTIMEOUT31ms
Bus Fr ee Tim e Betw een a S TOP and a S TART C ond i ti ontBUF1.3µs
Hold Time, (Repeated) START ConditiontHD,STA0.6µs
Repeated START Condition Setup TimetSU,STA0.6µs
STOP Condition Setup TimetSU,STO0.6µs
Data Hold TimetHD,DAT(Note 3)0.9µs
Data Setup TimetSU,DAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.7µs
Rise Time of Both SDA and SCL Signals, ReceivingtR(Notes 2, 4)20 + 0.1C b 300ns
Fall Time of Both SDA and SCL Signals, ReceivingtF(Notes 2, 4)20 + 0.1C b 300ns
Fall Time of SDA TransmittingtF.TX(Note 4)20 + 0.1C b 250ns
Pulse Width of Spike SuppressedtSP(Note 5)50nsap aci ti ve Load for E ach Bus Li neCb(Note 2)400pF
Note 1:All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:Guaranteed by design.
Note 3:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VILof the SCL signal) to bridge the
undefined region of SCL’s falling edge.
Note 4:Cb= total capacitance of one bus line in pF. tRand tFare measured between 0.3 x VDDand 0.7 x VDD.
Note 5:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(VDD= 3.3V, VLA= 3.3V, and TA= +25°C, unless otherwise noted.) (MAX7307)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (
MAX7306/7 toc01
INTERNAL OSCILLATOR OFF
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (
MAX7306/7 toc02
INTERNAL OSCILLATOR ON
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (
MAX7306/7 toc03
fSCL = 400kHz
PORT OPEN-DRAIN OUTPUT LOW VOLTAGE
vs. SINK CURRENT
SINK CURRENT (mA)
OUTPUT-VOLTAGE LOW (V)
MAX7306/7 toc04510152025
+125°C
+25°C
-40°C
PUSH-PULL OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
SOURCE CURRENT (mA)
OUTPUT-VOLTAGE HIGH (V)
MAX7306/7 toc05
-40°C
+25°C
+125°C
INTERNAL OSCILLATOR
vs. TEMPERATURE
TEMPERATURE (°C)
FREQUENCY (kHz)
MAX7306/7 toc06
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
2.00V/div
STAGGERED PWM OUTPUT
MAX7306/7 toc07
400μs/div
CL = 10pF
CL = 100pF
PUSH-PULL OUTPUT RISE TIME
MAX7306/7 toc08
20ns/div
2V/div
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Pin Description
PIN
MAX7306MAX7307NAMEFUNCTIONRST
Reset Input. RST is an active-low input, referenced to VDD, that clears the 2-wire interface,
which can be configured to put the device in the power-up reset condition and reset the
PWM and blink timing.2P1/INTInput/Output Port. P1/INT is configurable as an open-drain I/O or as a transition detection
interrupt output.3GNDGround4P2/OSCINInput/Output Port. P2/OSCIN is configurable as a push-pull I/O, open-drain I/O, or as the
PWM/blink/timing oscillator input.5P3/OSCOUTInput/Output Port. P3/OSCOUT is configurable as a push-pull I/O, open-drain I/O, or as
the PWM/blink/timing oscillator output.6P4Input/Output Port. P4 is configurable as a push-pull I/O or an open-drain I/O.VLAPort Supply for P1–P4. Connect VLA to a power supply between 1.40V and 5.5V. Bypass
VLA to GND with a 0.1µF capacitor.—AD0Address Input. Sets the device slave address. Connect to GND, VDD, SCL, or SDA to
provide four address combinations.VDDPositive Supply Voltage. Bypass VDD to GND with a 0.1µF ceramic capacitor.9SDASerial-Data I/O10SCLSerial-Clock Input—EPExposed Pad (µMAX only). Connect to GND.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Detailed Description
The MAX7306/MAX7307 4-port, general-purpose port
expanders operate from a 1.62V to 3.6V power supply.
Ports P2 through P4 can be configured as inputs, push-
pull outputs, and open-drain outputs. Port P1 can be
configured as an input and an open-drain output; P1
can also be configured to function as an (INT) output.
Each port configured as an open-drain or push-pull
output can sink up to 25mA. Push-pull outputs also
have a 10mA source drive capability. The MAX7306/
MAX7307 are rated to sink a total of 100mA into any
combination of the output ports. Output ports have
PWM and blink capabilities, as well as logic drive.
Initial Power-Up
On power-up, the MAX7307 default configuration has
all ports configured as input ports with logic levels ref-
erenced to VLA. The MAX7306 default configuration
has all ports configured as input ports with logic levels
referenced to VDD. The transition detection interrupt
status flag resets and stays high (see Tables1 and 2).
Device Configuration Registers
The device configuration registers set up the interrupt
function, serial-interface bus timeout, PWM/blink, oscil-
lator options, global blink period, and reset options
(see Tables3 and 4).
I2C
OUTPUT
LOGICI/OP1–P4
I/O
CONTROL
REGISTER
BANK
MAX7307 ONLY
INPUT
LOGIC
SDA
SCL
MAX7306 ONLY
VLAVDD
AD0
RST
MAX7306/
MAX7307
Block Diagram
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
REGISTER DATAREGISTERPOWER-UP CONDITIONADDRESS
CODE (hex)D7D6D5D4D3D2D1D0
Ports P1–P4Ports P_ are VLA referred input ports with interrupt
and debounce disabled0x01–0x0410000000
Configuration 26RST d oes not r eset r eg i ster s or counters; b l i nk p er i od s 1H z; tr ansi ti on fl ag cl ear ; i nterr up t status fl ag cl ear 0x2611101100
Configuration 27Ports P1–P4 are GPIO ports; bus timeout is
disabled0x2710001111
Table 2. Power-Up Register Status
REGISTERADDRESSAUTOINCREMENT ADDRESSPOR STATE
Port P1 or INT Output0x010x020x80
Port P2 or OSCIN Input0x020x030x80
Port P3 or OSCOUT Output0x030x040x80
Port P40x040x05*0x80
Configuration 260x260x270xEC
Configuration 270x270x28*0x8F
FACTORY RESERVED (Do not write to these registers)0x3C–0x3F0x3F–0x400x00
FACTORY RESERVED (Do not write to these registers)0x000x010x80
Table 1. Register Address Map
*No registers are present.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
REGISTER BITDESCRIPTIONVALUEFUNCTIONAn interrupt has occurred on at least one interrupt enabled input port.D7Interrupt Status
Flag (Read-Only)1*No interrupt has occurred on an interrupt enabled input port.Transition has occurred on an input port.D6Transition Flag
(Read-Only)1*No transition has occurred on an input port.Reserved0Reserved.
D4, D3, D2Blink Prescaler Bits0/1See Table 9 for blink frequency setting.RST does not reset PWM/blink counters.D1RST Timer1RST resets PWM/blink counters.RST does not reset registers to power-on-reset state.D0RST POR1RST resets registers to power-on-reset state.
Table 3. Configuration Register (0x26)
*Default state.
REGISTER BITDESCRIPTIONVALUEFUNCTIONEnables the bus timeout feature.D7Bus Timeout1*Disables the bus timeout feature.
D6, D5, D4Reserved0Reserved.Sets P3 to output the oscillator.D3P3/OSCOUT1*Sets P3 as a GPIO controlled by register 0x03.Sets P2 as the oscillator input.D2P2/OSCIN1*Sets P2 as a GPIO controlled by register 0x02.Sets P1 as the interrupt output.D1P1/INT Output1*Sets P1 as a GPIO controlled by register 0x01.Input Transition0Set to 0 on power-up for proper transition detection.
Table 4. Configuration Register (0x27)
*Default state.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Slave Address
The MAX7307 is set to slave address 0x98 and the
MAX7306 can be set to one of four I2C slave addresses
0x98 to 0x9F, using the address input AD0 (see Table5)
and is accessed over an I2C or SMBus serial interface.
The MAX7306 slave address is determined on each I2C
transmission, regardless of the transmission actually
addressing the device or not. The MAX7306 distin-
guishes whether address input AD0 is connected to
SDA, SCL, VDD, or GND during the transmission.
Therefore, the MAX7306 slave address can be config-
ured dynamically in an application without toggling the
device supply.
I/O Port Registers
The port I/O registers set the I/O ports, one register per
port (see Tables6 and 7). Use the I/O port registers to
configure the ports individually as inputs, open-drain, or
push-pull outputs. Port P1 can only be configured as an
input or an open-drain output. The push-pull bit (D6) set-
ting for the port I/O register P1 is ignored.
I/O Input Port
Configure a port as an input by writing a logic-high to the
MSB (bit D7) of the port I/O register (see Table6). To
obtain the logic level of the port input, read the port I/O
register bit, D0. This readback value is the instantaneous
logic level at the time of the read request if debounce is
disabled for the port (port I/O register bit D2 = 0), or the
debounced result if debounce is enabled for the port
(port I/O register bit D2 = 1). See Figure 1 for input port
structure.
I/O Output Port
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. The device reads
back the logic level, PWM, or the blink setting of the port
(see Table7).
DEVICE ADDRESSAD0O NN EC TIO N A6A5A4A3A2A1A0R /W
GND10011000/1
VDD10011010/1
SCL10011100/1
SDA10011110/1
Table 5. Slave-Address Selection
REGISTER BITDESCRIPTIONVALUEFUNCTIONPort I/O Set Bit1Sets the I/O port as an input.Refers the input to the VLA supply voltage.D6*Port Supply
Reference1Refers the input to the VDD supply voltage.Disables the transition interrupt.D5Transition Interrupt
Enable1Enables the transition interrupt.
D4, D3Reserved0Do not write to these registers.Disables debouncing of the input port.D2Debounce1Enables debouncing of the input port.No transition has occurred since the last port read.D1Port Transition
State (Read-Only)1A transition has occurred since the last port read.Port input is logic-low.D0Port Status
(Read-Only)1Port input is logic-high.
Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01 to 0x04)
*Bit D6 controls the I/O’s supply reference for the MAX7307. The MAX7306 ignores bit D6.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
DEBOUNCE LOGIC
TRANSITION
DETECTION
TRANSITION
DETECTION
I/O
MAX7307 ONLY
PORT_[2]
(DEBOUNCE)
INTERRUPT
LOGIC
INT
INT2
INT4
INT
PORT_ [5]
INTERRUPT
ENABLE
PORT_[0]
(PORTIN)
PORT_[6]
(THRESHOLD
SELECT)1
VDDVLA
Figure 1. Input Port Structure
REGISTER BITDESCRIPTIONVALUEFUNCTIONPort I/O Set Bit0Sets the I/O port as an output.Sets the output type to open-drain.
Output Port Set to
Push-Pull
or Open-Drain1Sets the output type to push-pull.Sets the output to PWM mode.D5PWM/Blink Enable1Sets the output to blink mode.MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.D4Duty Cycle Bit 41MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.D3Duty Cycle Bit 31Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.D2Duty Cycle Bit 21Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.D1Duty Cycle Bit 11Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.D0Duty Cycle Bit 01LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Table 7. Port I/O Registers (I/O Port Set as an Output, Registers 0x01 to 0x04)
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Port Supplies and Level Translation
The MAX7307 features a port supply, VLA, that provides
the logic supplies to all push-pull I/O ports. P2 through
P4 can be configured as push-pull I/O ports (see Figure
3). VLApowers the logic-high port output voltage sourc-
ing the logic-high port load current. VLAprovides level
translation capability for the outputs and operates over a
1.40V to 5.5V voltage independent of the power-supply
voltage, VDD.
Each port of the MAX7307 set as an input can be config-
ured to switch midrail of either the VDDor the VLAport
supplies. Whenever the port supply reference is
changed from VDDto VLA, or vice versa, read the port
register to clear any transition flag on the port.
Ports P2 through P4 are overvoltage protected to VLA.
This is true even for a port used as an input with a VDD
port logic-input threshold. Port P1 is overvoltage pro-
tected to 5.5V, independent of VDDand VLA(see Figure
3). To mix logic outputs with more than one voltage
swing on a group of ports using the same port supply,
set the port supply voltage (VLA) to be the highest out-
put voltage. Use push-pull outputs and port P1 for the
highest voltage ports, and use open-drain outputs with
external pullup resistors for the lower voltage ports. For
the MAX7307, when P2, P3, and P4 ports are acting as
an input referenced to VDD, make sure the VLAvoltage
is greater than VDD- 0.3V.
SELECT
VDDVLA
INPUTPORT P1
OUTPUTP2, P3, P4
SELECT
VDDVLA
INPUTPORTS P2
THROUGH P4
MAX7307 ONLYMAX7307 ONLY
OUTPUT
Figure 3. Port I/O Structure
I/O
PORT_[5]CLOCK
5-BIT PWM
4-BIT BLINK3-BIT PRESCALER
PORT_[3:0]
PORT_[4:0]
CONFIG26 [4:2]
Figure 2. Output Port Structure

Partno	Mfg	Dc	Qty	Available	Descript
MAX7306ALB+T	MAXIM	N/a	13324	avai	SMBus/I²C Interfaced 4-Port, Level-Translating GPIOs and LED Drivers